Thread Rating:
  • 0 Vote(s) - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
A VHDL IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY
#1

A VHDL IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY

.pdf   A VHDL IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY.PDF (Size: 171.76 KB / Downloads: 29)
ABSTRACT
The increasing growth of sub-micron technology has resulted in the difficulty of testing. Design and test engineers have
no choice but to accept new responsibilities that had been performed by groups of technicians in the previous years.
Design engineers who do not design systems with full testability in mind open themselves to the increased possibility of
product failures and missed market opportunities. BIST is a design technique that allows a circuit to test itself. In this
paper, the test performance achieved with the implementation of BIST is proven to be adequate to offset the disincentive
of the hardware overhead produced by the additional BIST circuit. The technique can provide shorter test time
compared to an externally applied test and allows the use of low-cost test equipment during all stages of production.
Keywords: Built-In-Self-Test (BIST), UART, simulation, synthesis.
1.0 INTRODUCTION
Manufacturing processes are extremely complex, inducing manufacturers to consider testability as a requirement to
assure the reliability and the functionality of each of their designed circuits. One of the most popular test techniques is
called Built-In-Self-Test (BIST). A BIST Universal Asynchronous Receive/Transmit (UART) has the objectives of
firstly to satisfy specified testability requirements, and secondly to generate the lowest-cost with the highest performance
implementation. UART has been an important input/output tool for decades and is still widely used. Although BIST
techniques are becoming more common in industry, the additional BIST circuit that increases the hardware overhead
increases design time and performance degradation is often cited as the reason for the limited use of BIST [1].
This paper focuses on the design of a UART chip with embedded BIST architecture using Field Programmable Gate
Array (FPGA) technology. The paper describes the problems of Very-Large-Scale-Integrated (VLSI) testing followed by
the behavior of UART circuit using VHISC Hardware Description Language (VHDL). In the implementation phase, the
BIST technique will be incorporated into the UART design before the overall design is synthesized by means of
reconfiguring the existing design to match testability requirements. The UART is targeted at broadband modem, base
station, cell phone, and PDA designs.
2.0 VLSI TESTING PROBLEMS
Today’s highly integrated multi-layer boards with fine-pitch ICs are virtually impossible to be accessed physically for
testing. Traditional board test methods which include functional test, only accesses the board’s primary I/Os, providing
limited coverage and poor diagnostics for board-network fault. In circuit testing, another traditional test method works
by physically accessing each wire on the board via costly “bed of nails” probes and testers. To identify reliable testing
methods which will reduce the cost of test equipment, a research to verify each VLSI testing problems has been
conducted. The major problems detected so far are as follows:
a) Test generation problems;
b) The input combinatorial problems; and
c) The gate to I/O pin ratio problems.
A VHDL Implementation of UART Design with BIST Capability pp. 73 - 86
Malaysian Journal of Computer Science, Vol. 19 (1), 2006
74
2.1 Test Generation Problems
The large number of gates in VLSI circuits has pushed computer automatic-test-generation times to weeks or months of
computation. The numbers of test patterns are becoming too large to be handled by an external tester and this has
resulted in high computation costs and has outstripped reasonable available time for production testing.
Another test generation problem is that computer algorithms providing Automatic Test Pattern Generation (ATPG) work
well for combinatorial logic but rather poorly for sequential logic circuits. Sequential circuits demand too much
computer memory and computation since many more time states must be evaluated [2a].
2.2 The Input Combinatorial Problem
A combinatorial logic circuit with N primary input nodes has a total set of 2N possible input vectors. This is the number
of test vectors required to exhaustively test a circuit for those functions that a customer might use. In contrast to MSI
(Medium-Scale-Integrated) circuits, the number of test vectors needed to exhaustively examine a VLSI circuit such as
32-bits microprocessor is prohibitive. However, a finite number of test vectors can still be applied to an IC and follow
the economic rules of production. The finite number of test vectors is much lesser than the full exhaustive test set of a
VLSI circuit [2a].
2.3 The Gate to I/O Pin Ratio Problem
As ICs grow in gate counts, it is no longer true that most gate nodes are directly accessible by one of the pins on the
package. This makes testing of internal nodes more difficult as they could neither no longer be easily controlled by
signal from an input pin (controllability) nor easily observed at an output pin (observe ability). Pin counts go at a much
slower rate than gate counts, which worsens the controllability and observe ability of internal gate nodes [2a].
The VLSI testing problems described above have motivated designers to identify reliable test methods in solving these
difficulties. An insertion of special test circuitry on the VLSI circuit that allows efficient test coverage is the answer to
the matter. The need for the insertion has been addressed by the need for design for testability and hence the need for
BIST.
3.0 VHDL AND BIST
It is increasingly common for design for testability (DFT) issues to be addressed at design reviews prior to circuit tapeout
approval. Previously, in the age of schematics, this often requires design and test engineers to sift through pages of
manuals and data sheets looking for things like asynchronous set/reset circuit configurations, derived or internally
generated clocks, and combinatorial and sequential feedback loops. The review inevitably occurred late in the design
cycle; adversely affecting project schedules if glitches were found, and making for an uncomfortable process for the
circuit designer. However, with today's design practices, schematics are mostly outdated [3]. Designers can take more
control of the DFT review by performing DFT rule checking at the register transfer language (RTL) (VHDL) level.
Nevertheless, finding DFT problems in language-based designs is still not a simple task for humans.
The acceptance of the design for test techniques has been largely due to the possibility of VHDL support to this design
style. It is desirable to eventually have available a BIST approach with similarly VHDL support. The high degree of
standardization makes it possible to have most testability feature previously added to a design using VHDL [4] [5].
4.0 UNIVERSAL ASYNCHRONOUS RECEIVE/TRANSMIT (UART)
Serial data is transmitted via its serial port. A serial port is one of the most universal parts of a computer. It is a
connector where serial line is attached and connected to peripheral devices such as mouse, modem, printer and even to
another computer. In contrast to parallel communication, these peripheral devices communicate using a serial bit stream
A VHDL Implementation of UART Design with BIST Capability pp. 73 - 86
Malaysian Journal of Computer Science, Vol. 19 (1), 2006
75
PC
PC
protocol (where data is sent one bit at a time). The serial port is usually connected to UART, an integrated circuit which
handles the conversion between serial and parallel data [6] [7].
Fig. 1 shows how the UART receives a byte of parallel data and converts it to a sequence of voltage to represent 0s and
1s on a single wire (serial). To transfer data on a telephone line, the data must be converted from 0s and 1s to audio
tones or sounds (the audio tones are sinusoidal shaped signals). This conversion is performed by a peripheral device
called a modem (modulator/demodulator). The modem takes the signal on the single wire and converts it to sounds. At
the other end, the modem converts the sound back to voltages, and another UART converts the stream of 0s and 1s back
to bytes of parallel data.
Fig. 1: Serial Data Transmission and Receive
5.0 THE FEATURES
Fig. 2: UART with BIST top level design symbol
Table 1 describes the function and the description of all UART pins available at the top-level design (Fig. 2) of the
VHDL implementation. The UART are capable of the following [8]:
a) Fully programmable serial interface characteristics:
Reply

Marked Categories : implementation of uart with bist capability, ppt on vhdl implementation of uart design with bist capability, uart in verilog malaysian journal 2012, a verilog impimentation of uart design with bist capability, vhdl implementation of bist in uart design, uart vhdl ppt, vhdl uart serial, pcb layout of vhdl implementation using uart with bist capability, ppt on vlsi project uart based with bist, vhdl uart, seminar report of vhdl description of self checking logic ckt,

[-]
Quick Reply
Message
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  JPEG Decoder Design Report seminar flower 1 3,220 25-03-2018, 06:49 PM
Last Post: magnumZ
  Design and Implementation of High-Performance FPGA Signal Processing Datapaths seminar class 1 300,467 20-09-2017, 01:31 PM
Last Post: jaseela123
  A Design & Implementation of Collision Avoidance System (CAS) for Automobiles seminar flower 1 1,099 19-09-2017, 04:25 PM
Last Post: jaseela123
  DESIGN AND PERFORMANCE ANALYSIS OF OPTICAL CDMA SYSTEM USING NEWLY DESIGNED MULTIWAVE project girl 1 1,231 15-09-2017, 01:34 PM
Last Post: jaseela123
  Cooperative Caching in Wireless P2P Networks: Design, Implementation, And Evaluation seminar code 1 587 02-09-2017, 12:26 PM
Last Post: jaseela123
  SECURITY ANALYSIS AND IMPLEMENTATION OF 3-LEVEL SECURITY SYSTEM USING IMAGE REPORT study tips 1 1,010 31-08-2017, 01:15 PM
Last Post: jaseela123
  DESIGN AND CONSTRUCTION OF DOOR LOCKING SECURITY SYSTEM USING GSM project maker 1 538 29-08-2017, 09:36 AM
Last Post: jaseela123
  IMPLEMENTATION OF BREADTH FIRST SEARCH USING GRAPH SEARCH ALGORITHMS. mkaasees 0 240 25-08-2017, 09:32 PM
Last Post: mkaasees
  Implementation Of A Functional Language nit_cal 0 9,414,298 25-08-2017, 09:32 PM
Last Post: nit_cal
  Implementation of Multipath Routing In AODV For Wireless Ad-hoc Networks nit_cal 0 18,327,134 25-08-2017, 09:32 PM
Last Post: nit_cal
This Page May Contain What is A VHDL IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY And Latest Information/News About A VHDL IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY,If Not ...Use Search to get more info about A VHDL IMPLEMENTATION OF UART DESIGN WITH BIST CAPABILITY Or Ask Here

Options: