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Tags: Losses, Conduction, Reduced, Factor, Power, Unity, With, Rectifier, SEPIC, Bridgeless, Bridgeless SEPIC Rectifier With Unity Power Factor and Reduced Conduction Losses,
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Bridgeless SEPIC Rectifier With Unity Power Factor and Reduced Conduction Losses
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Abstract—In this paper, a new bridgeless single-phase ac–dc
converter with an automatic power factor correction (PFC) is
proposed. The proposed rectifier is based on the single-ended
primary inductance converter (SEPIC) topology and it utilizes a
bidirectional switch and two fast diodes. The absence of an input
diode bridge and the presence of only one diode in the flowingcurrent
path during each switching cycle result in less conduction
loss and improved thermal management compared to existing PFC
rectifiers. Other advantages include simple control circuitry, reduced
switch voltage stress, and low electromagnetic-interference
noise. Performance comparison between the proposed and the
conventional SEPIC PFC rectifier is performed. Simulation and
experimental results are presented to demonstrate the feasibility
of the proposed technique.

I N RECENT years, the demand for improving power quality
of the ac system has become a great concern due to the
rapidly increased numbers of electronic equipment. To reduce
harmonic contamination in power lines and improve the transmission
efficiency, power factor correction (PFC) research became
an active topic in power electronics, and significant efforts
have been made on the developments of the PFC converters
[1]–[4]. As a matter of fact, the PFC circuits are becoming
mandatory on single-phase power supplies as more stringent
power quality regulations and strict limits on the total harmonic
distortion (THD) of input current are imposed [5].
The preferable type of PFC is active PFC since it makes
the load behave like a pure resistor, leading to near-unity load
power factor and generating negligible harmonics in the input
line current [6]. Most active PFC circuits as well as switchedmode
power supplies in the market today comprise a front-end
bridge rectifier, followed by a high-frequency dc–dc converter
such as a boost, a buck–boost, a Cuk, a single-ended primary
inductance converter (SEPIC), and a flyback converter. This
approach is suitable for a low-to-medium power range. As the
power level increases, the high conduction loss caused by the
high forward voltage drop of the diode bridge begins to degrade
the overall system efficiency, and the heat generated within the bridge rectifier may destroy the individual diodes. Hence,
it becomes necessary to utilize a bridge rectifier with higher
current-handling capability or heat-dissipating characteristics.
This increases the size and cost of the power supply, which is
unacceptable for an efficient design. Another reason for high
conduction losses in conventional active PFC circuits is due to
the fact that during each switching cycle, there are always three
power semiconductors in the flowing-current path (two slowrecovery
diodes plus an active switch or a fast-recovery diode).
In an effort to improve the power supply efficiency, a number
of bridgeless PFC circuit topologies have been proposed
[7]–[24]. All the presented bridgeless topologies so far implement
a boost-type circuit configuration (also referred to as
dual-boost PFC rectifiers) because of its low cost and its high
performance in terms of efficiency, power factor, and simplicity.
In [25], a systematic review of the bridgeless PFC boost
rectifier implementations that have received the most attention
is presented along with their performance comparison with the
conventional PFC boost rectifier. A simplified schematic of the
conventional bridgeless PFC boost rectifier is shown in Fig. 1.
The switching conduction sequences for the rectifier of Fig. 1
are as follows: 1) during positive ac line cycle, Q1 − Dq2,
D1 − Dq2, and 2) during negative ac line cycle, Q2 − Dq1,
D2 − Dq1. Thus, during each switching cycle, the current path
goes through only two semiconductor devices instead of three.
As a result, the total conduction losses on the semiconductor devices
will be considerably lower compared to the conventional
PFC boost rectifier. These features have led power supply companies
to start looking for bridgeless PFC circuit topologies.
Although the bridgeless boost rectifier is very simple and
popular, it has the same major practical drawbacks as the
conventional boost converter. These drawbacks are that the
dc output voltage is always higher than the peak input voltage,
input–output isolation cannot be easily implemented, high
startup inrush current, as well as a lack of current limiting
during overload conditions. Moreover, it is well known that

the boost converter operating in discontinuous current mode
(DCM) can offer a number of advantages, such as inherent
PFC function, very simple control, soft turn-on of the main
switch, and reduced diode reversed-recovery losses. However,
the DCM operation requires a high-quality boost inductor since
it must switch extremely high peak ripple currents and voltages.
As a result, a more robust input filter must be employed to
suppress the high-frequency components of the pulsating input
current, which increases the overall weight and cost of the
In order to overcome these problems, a new bridgeless PFC
circuit based on the SEPIC topology is introduced in this paper.
Unlike the boost converter, the SEPIC and Cuk converters offer
several advantages in PFC applications, such as easy implementation
of transformer isolation, inherent inrush current limitation
during startup and overload conditions, lower input current
ripple, and less electromagnetic interference (EMI) associated
with the DCM topology [26]–[30]. The proposed bridgeless
SEPIC rectifier is shown in Fig. 2(a). This circuit is formed by
connecting two SEPICs, one with a positive input source and
the other having an inverted input source. The proposed rectifier
utilizes a bidirectional switch and two fast diodes. However,
the two power switches, namely, Q1 and Q2, can be driven with the same PWM signal, which significantly simplifies the
implementation of the control circuit. The operational circuits
during a positive and a negative half-line cycle are shown in
Fig. 2(b) and ©, respectively. Note that during each switching
cycle, there is either one or two semiconductors in the flowingcurrent
path; hence, the conduction losses as well as the thermal
stresses on the semiconductor devices are further reduced,
and the circuit efficiency is improved compared with that
of the bridgeless boost rectifier. Another advantage of the proposed
rectifier is a reduction in the semiconductor voltage stress
as compared with that of the conventional SEPIC PFC rectifier.
The voltage stress is reduced to a level that is comparable
with that of the PFC boost rectifier. On the other hand, components’
current stresses are comparable with their counterparts
in the conventional SEPIC. The proposed rectifier structure utilizes
three inductors, which are often described as a disadvantage.
However, the three inductors can be coupled on the same
magnetic core [31], allowing considerable size and cost reduction,
and additionally, the “near-zero-ripple-current” condition
at the input port of the rectifier can be achieved without compromising
performance. This condition is very desirable, particularly
for the DCM operation, because the generated EMI noise
is minimized, reducing input filtering requirements dramatically.
Moreover, both the conventional SEPIC PFC rectifier and
the proposed rectifier of Fig. 2(a) have the same count of total
components when the coupled inductor technique is implemented.
The major drawback of the proposed bridgeless SEPIC
PFC rectifier in Fig. 2(a) is that it requires an additional gatedrive
The remainder of this paper is organized as follows. Principle
of operation and theoretical analysis are presented in
Section II. Detailed analysis, modeling, and comparisons are
presented in Section III. A simplified design procedure example
and simulation results are included in Section IV. Section V
provides a detailed analysis of the proposed converter with
coupled inductors. Finally, results from a laboratory prototype
and conclusion are given in Sections VI and VII, respectively.
The operation of the converter will be explained assuming
that the three inductors are working in DCM. Operating the
SEPIC in DCM offers advantages over continuous-currentmode
(CCM) operation, such as a near-unity power factor
can be achieved naturally and without sensing the input line
current [26]. Also, in DCM, both Q1 and Q2 are turned on
at zero current, while diodes Do1 and Do2 are turned off at
zero current. Thus, the loss due to the switching losses and the
reverse recovery of the rectifier are considerably reduced.
The theoretical analysis of the proposed rectifier is performed
during one switching period in a positive half-period of the
input voltage [Fig. 2(b)]. Similar to the conventional SEPIC and
Cuk converters, the DCM for the proposed rectifier occurs when
the current through diode Do1 drops to zero before the end of
the switch-off time. Thus, the circuit operation in one switching
cycle, Ts, can be divided into three stages, as shown in Fig. 3. To
simplify the analysis, it is assumed that the rectifier

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