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design of configurable ofdm data processor for wimax
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The heterogeneous on-chip multiprocessor system (MP-SoC) promises better computing performance while keeping the dissipation power low. This feature is well suited for the wireless communication system where power consumption becomes a vital consideration. This document presents a new flexible data exchange architecture for the WiMAX MPSoC baseband incorporating the intermediate processor (IPC), multiprocessor, multi-bus, multifrequency and parallel processing process of the medium access controller layer (MAC). This WiMAX MPSoC based on the RISC processor with the AMBA multi-bus system operates on a heterogeneous frequency of 40 MHz and 120 MHz. The system has been implemented and verified with the Altera Stratix FPGA board. The verification result shows that the system can operate in real time with a maximum performance of 11 MBps using only the 40 MHz system clock.

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