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Direct Memory Access
Post: #1

The Idea Of Direct Memory Access
By providing circuitry to generate addresses and memory control signals independently of the processor we see that it is possible to improve performance considerably. All that is necessary is to provide a signal to tell the processor to remove itself from the bus so there is no contention on the memory control, address, or data lines.

This is the entire concept behind direct memory access (DMA). To complete our picture, it is important to note that there are actually several ways that DMA can be done. In particular, there are three common choices:-

burst mode DMA :- In burst mode the DMA controller transfers an entire block of data without interruption. During the time of the transfer, the DMA controller retains complete control of the processor's bus.

Cycle Stealing :- If it is desirable to let the processor do some processing while the DMA controller transfers data cycle stealing can be used. In this case, the DMA controller will periodically request use of the bus until all of its data are transferred. This slows down the processor and the DMA transfer.

Transparent DMA :- It is possible for the DMA controller to monitor the internal status of the processor. In those cases where the processor does not need bus access (internal data moves and such) the DMA controller uses the bus. This slows down the DMA transfer, but not the processor.

The proper transfer mode to use is determined by the system requirements.

Burst Mode DMA
Burst mode DMA is a typical way of handling bulk data transfers (like the idea we described for our video controller). The other modes operates in a similar fashion. For a burst mode transfer:-

1) The processor loads the DMA controller with the start address of the destination in memory and the number of words to transfer.

2) When the device delivering or requesting data is ready, the DMA controller is signaled. In turn, the
controller signals the processor that a DMA transfer is pending.

3) The processor acknowledges the request, finishes its current instruction, and then floats the address, control, and data buses.

4) The DMA controller now provides address and control signals to memory while the device requesting the transfer supplies or receives the data.

5) Once the transfer is complete, the DMA signals the processsor to resume its normal operation.

The signaling of the 8088 processor is done through the hold and holda lines. When the DMA controller wants the bus, it signals the processor by raising hold. After the processor completes the current
instruction, it tri-states the data, address, and control lines, and raises hold acknowledge (holda). Once the DMA controller sees holda, it knows it is free to use the bus.
Post: #2
Direct Memory Access

.ppt  dma.ppt (Size: 383 KB / Downloads: 95)

What is DMA

Direct memory access (DMA) is a feature of modern computers and microprocessors that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. Many hardware systems use DMA including disk drive controllers, graphics cards, network cards and sound cards. DMA is used for transferring data between the local memory and the main memory. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel. Similarly a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time and allowing computation and data transfer concurrency


DMA is an essential feature of all modern computers, as it allows devices to transfer data without subjecting the CPU to a heavy overhead. Otherwise, the CPU would have to copy each piece of data from the source to the destination, making itself unavailable for other tasks. This situation is aggravated because access to I/O devices over a peripheral bus is generally slower than normal system RAM. With DMA, the CPU gets freed from this overhead and can do useful tasks during data transfer (though the CPU bus would be partly blocked by DMA). In the same way, a DMA engine in an embedded processor allows its processing element to issue a data transfer and carries on its own task while the data transfer is being performed.

DMA Operation

There are three independent channels for DMA transfers. Each channel receives its trigger for the transfer through a large multiplexer that chooses from among a large number of signals. When these signals activate, the transfer occurs.
The DMA controller receives the trigger signal but will ignore it under certain conditions. This is necessary to reserve the memory bus for reprogramming and non-maskable interrupts etc. The controller also handles conflicts for simultaneous triggers. The priorities can be adjusted using the DMA Control Register 1 (DMACTL1). When multiple triggers happen simultaneously, they occur in order of module priority. The DMA trigger is then passed to the module whose trigger activated. The DMA channel will copy the data from the starting memory location or block to the destination memory location or block. There are many variations on this, and they are controlled by the DMA Channel Control Register
Post: #3
Direct Memory Access

.pdf  dma pddf.pdf (Size: 153.22 KB / Downloads: 128)


In the discussion on computer architecture and the role of the Central Processing Unit a brief description was given
on how the CPU may transfer data to or from a number of external (other than memory) devices. The operation
treated the I/O system for reading and writing in the same manner as memory, using address, data lines and WR
RD control lines. This requires CPU intervention and is costly in "time".
Direct Memory Access--the ability of an I/O subsystem to transfer data to and from a memory subsystem without
processor intervention.
DMA Controller--a device that can control data transfers between an I/O subsystem and a memory subsystem in the
same manner that a processor can control such transfers.

DMA Controller

The DMA controller can issue commands to the memory that behave exactly like the commands issued by the
CPU. The DMA controller in a sense is a second processor in the system but is dedicated to an I/O function. The
DMA controller as shown below connects one or more I/O ports directly to memory, where the I/O data stream
passes through the DMA controller faster and more efficiently than through the processor as the DMA channel is
specialised to the data transfer task.

The DMA interface

The DMA adds one more level of complexity to the I/O interface because a DMA controller has independent
access to memory. One set of wires (bus) can carry at most one transaction at a time. If the DMA and a
microprocessor share the signal wire to memory there must be a mechanism to arbitrate which shall have access to
memory when both attempt to at the same time.

Functional behaviour of a DMA transaction

1. The processor transmits the following information to a DMA controller:
(a) beginning address in memory
(b) block length (number of words to transfer)
© direction (memory-to-device or device-to-memory)
(d) port ID
(e) end of block action (interrupt request or no interrupt request).
Post: #4

.ppt  1DIRECT MEMORY.ppt (Size: 350.5 KB / Downloads: 265)


An important aspect governing the Computer System performance is the transfer of data between memory and I/O devices.
The operation involves loading programs or data files from disk into memory, saving file on disk, and accessing virtual memory pages on any secondary storage medium.
Consider a typical system consisting of a CPU ,memory and one or more input/output devices as shown in fig. Assume one of the I/O devices is a disk drive and that the computer must load a program from this drive into memory.
The CPU would read the first byte of the program and then write that byte to memory. Then it would do the same for the second byte, until it had loaded the entire program into memory.

Implementing DMA in a Computer System

A DMA controller implements direct memory access in a computer system.
It connects directly to the I/O device at one end and to the system buses at the other end. It also interacts with the CPU, both via the system buses and two new direct connections.
It is sometimes referred to as a channel. In an alternate configuration, the DMA controller may be incorporated directly into the I/O device.

Data Transfer using DMA Controller

To transfer data from an I/O device to memory, the DMA controller first sends a Bus Request to the CPU by setting BR to 1. When it is ready to grant this request, the CPU sets it’s Bus grant signal, BG to 1.
The CPU also tri-states it’s address,data, and control lines thus truly granting control of the system buses to the DMA controller.
The CPU will continue to tri-state it’s outputs as long as BR is asserted.

Internal Configuration

The DMA controller includes several registers :-
The DMA Address Register contains the memory address to be used in the data transfer. The CPU treats this signal as one or more output ports.
The DMA Count Register, also called Word Count Register, contains the no. of bytes of data to be transferred. Like the DMA address register, it too is treated as an O/P port (with a diff. Address) by the CPU.
The DMA Control Register accepts commands from the CPU. It is also treated as an O/P port by the CPU.

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