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JPEG Decoder Design Report
Post: #1

JPEG Decoder Design

.doc  JPEG Decoder.doc (Size: 3.09 MB / Downloads: 107)


Since modern computer systems are required to store and transmit vast amounts of data the field of data compression has become very important. One form of data that is commonly processed by computer systems is graphic images. To compress graphic images the Joint Photographic Experts Group (JPEG) developed a method of compressing images by reducing the precision of the high-frequency portions of images. This allows the images to be stored more compactly without sacrificing the important low-frequency portions.
This is done by first dividing the image into an array of 8 pixels by 8 pixels data blocks and performing a transformation on these data blocks that expresses each data block by a linear combination of sinusoidal components of harmonic frequencies. Then the magnitudes of the components corresponding to the higher frequency harmonics are stored with less precision then the lower frequencies. This filtering loses some of the detail of the image but retains most of the image’s information since the human eye acts as an integrator, which reduces the contribution of high detail portions of our visual field. After being filtered the data is coded so that large values will be stored with larger numbers of bits then smaller values. This process allows a variable length coding of the data for compression. Finally the data is Huffman coded so that more frequent data values are stored as shorter codes
This algorithm for image compression is formally known as ISO10918-1 but is commonly referred to as JPEG after the standardization body that developed it. JPEG is frequently used both on the Internet and in consumer electronics devices such as digital cameras. To decode JPEG images into uncompressed data commonly stored as Bitmaps, which are a device independent representation of the array of pixels that make up an image a device called a JPEG decoder, is needed to restore the image. This device performs the inverse of the JPEG encoder, which encodes bitmap images as JPEG streams. Usually JPEG encoders and decoders are written as programs in a high-level language such as C or C++ and run on general-purpose microprocessors.
The purpose of this project is to design and implement a JPEG decoding system that can be incorporated into a digital camera design. This application requires the JPEG decoder to be simple, fast, low power, and easily integrated into a larger system. Such systems have been built before and are commonly used in consumer electronics devices such as digital cameras. Also JPEG decoder designs such as the one built for this project are available for purchase and can be incorporated into larger designs.

Problem Statement

This project involved the design of a JPEG decoder. JPEG, the Joint Photographic Expert Group, is a standardization body that produces standards for continuous tone image coding. Perhaps the best known such standard is IS10918-1 which is a widely used image compression standard. The JPEG decoder designed in this project will be used to decode a JPEG File Interchange Format (JFIF) file into an uncompressed bitmap file. JFIF is the file format that is commonly associated with JPEG and is used widely on the Internet and in consumer electronics devices to store still image data. While the JPEG standard (ISO 10918-1) defines a large class of related compression algorithms the JPEG decoder designed for this project will focus on the simplest and most widely used such algorithm known as baseline JPEG.
The wide use of JPEG in consumer electronics devices such as digital cameras produces a need for a fast, low-power implementation that is capable of meeting the demands of the overall system. As with any digital system the JPEG decoder could be implemented either in software running on a general purpose microprocessor, or more likely a special purpose microprocessor such as a Digital Signal Processor, DSP, or with custom hardware circuitry. The advantages and disadvantages of both software and hardware implementations will be discussed shortly. While this project will produce only the JPEG decoder much of the design would be reusable in the design of a JPEG encoder.
This project will demonstrate the JPEG decoder using a Field Programmable Gate Array (FPGA). The FPGA will be programmed with the JPEG decoder design and will receive input JPEG images from a serial communication link with a computer system and send the decoded output images back to the computer for viewing.


It is desirable to maximize the JPEG decoder’s speed. While again the speed of the circuit is highly dependent on implementation technology the JPEG decoder must be able to perform at speeds between the speed of a software implementation of JPEG decoding and the speed of a fully optimized JPEG decoder design that is available commercially. While speed is a crucial design point in a production design it will not be emphasized in this prototype using an FPGA while the design should be suitable for optimization towards a specific usage.


Lastly the power consumption of the JPEG decoder must be within acceptable limits. However since the power consumed is determined by the FPGA used not the design itself only simulation data will be available to measure the predicted actual power consumption of the JPEG decoder when implemented using as an ASIC (Application Specific Integrated Circuit).

Alternate Solutions Analysis

As previously mentioned a digital system can be implemented either in software running on a microprocessor or with a custom designed digital logic circuit. These are the major realms of digital system design; each of these solutions has a wide variety of design decisions associated with them.

Software Implementation

Implementation of the JPEG decoding algorithm in software is very common. There are numerous open-source software implementations of JPEG in languages such as C and C++. The existence of this software and the easy accessibility to C compilers for most microprocessor designs simplifies the software design to the point where only moderate coding would be required to modify one of these implementations for a specific use. Since microprocessors are relatively affordable at low volumes such an implementation would be essential for a small volume product. In some applications that use a microprocessor it would be reasonable to bear the extra load of JPEG decoding on the microprocessor but in many situations the microprocessor is a valued resource that would better be utilized performing other calculations.

Hardware Implementation

The repetitive, well defined nature of the process of JPEG decoding lends itself very well to a hardware implementation where the ease of design and implementation are traded off for a faster, less power consuming solution which allows greater computational flexibility at the cost of design effort. In addition to these conventional arguments for a hardware implementation the constantly expanding area of chips produced by the continual progress of Moore’s Law, which states that chip capacity will double every 18 months, provides another reason to consider a hardware implementation of JPEG decoding. The increased chip capacity has allowed, in recent years, the combination of a general-purpose microprocessor with custom logic units on a single chip. By placing these external units on the same piece of silicon as the microprocessor the costs of communications are greatly reduced. As the capacity of integrated circuits continues to increase such System-On-a-Chip designs will continue to grow in popularity.

VHDL – VHSIC Hardware Description Language

VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) is a powerful language used for the description of digital circuits. VHDL allows the mixture of both high-level behavioral descriptions and low-level structural descriptions to be connected and used together. Using these multiple levels of abstraction together allows the design process to focus on testing functionality and then optimizing the critical areas of the design by specifying them at a more detailed level where the designer can optimize the circuit as needed to meet specifications

Engineering Analysis

The relationships between layout tools, schematic capture tools, and hardware description languages are very closely analogous to the corresponding relationships in software between machine languages, assembly languages, and programming languages.
Just as the current focus in software design is on reusable, machine independent algorithmic descriptions the use of a technology independent description language such as VHDL or Verilog are strongly preferred. The effort expended on designing HDL descriptions of digital circuits can be reused and optimized as logic synthesis tools become more powerful. This potential for improving designs through the advancement of synthesis tools and implementation technologies makes the design of large libraries of digital designs to be designed and reused as software libraries are today. This concept of a design, described in an HDL, has been termed Intellectual Property or IP which conveys the great potential importance of reusable designs.
For all these reasons digital system design in a High-Level Description Language is becoming the preferred method for design of hardware and the relative ease of this design in an HDL is comparable to software implementation in a High-Level Programming Language such as C and C++.
Post: #2
Why I can't found any source codes ? I need to purchase it?

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