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Low Power, Energy- efficient Domino Logic Circuits

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Low Power, Energy- efficient Domino Logic Circuits

Salendra.Govindarajulu1, Dr.T.Jayachandra Prasad2
1Associate Professor, ECE, RGMCET, JNTU

Sub-threshold leakage power is soon expected to dominate the total power consumed by a CMOS circuit in deep submicron ( DSM ) technology. Circuit techniques aimed at lowering leakage currents are therefore highly desirable. In this work, low power CMOS designs using dual threshold voltage ( dual-Vt ) domino logic are proposed. Single threshold voltage ( single-Vt ), standard dual-Vt and modified dual-Vt domino logic circuits regarding power and speed are compared. These design styles are compared by performing detailed transistor-level simulations on bench mark circuits using DSCH3 and Microwind3 CAD tool.
It is envisaged that sub-threshold leakage power will dominate the total power consumed by a CMD circuit in deep submicron technology (DSM). Circuit techniques designed to reduce leakage currents are therefore highly desirable. In this work, we propose low power CMOS designs with dual domino voltage logic (dual-Vt). Dual-threshold (single-Vt), double-Vt and double-Vt-modified logic circuits are compared with respect to power and speed. These design styles are compared by performing transistor-level simulations detailed in reference circuits using the DSCH3 tool and Microwind3 CAD.

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