Important: Use custom search function to get better results from our thousands of pages

Use " " for compulsory search eg:"electronics seminar" , use -" " for filter something eg: "electronics seminar" -"/tag/" (used for exclude results from tag pages)

Tags: MULTISENSOR, STRATEGIES, SUPPORT, BLIND, PEOPLE A, CLEAR PATH, INDICATOR, MULTISENSOR STRATEGIES TO SUPPORT BLIND PEOPLE A CLEAR PATH INDICATOR, multisensor strategies to assist blind people a clear path indicator, multisensor strategies to assist blind people,
Thread Rating:
  • 0 Votes - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
Post: #1

Abstract :
The development of electronic sensing devices for the visually impaired requires knowledge of the needs and abilities of this class of people. In this project we present a rough analysis that can be used to properly define the criteria to be adopted for the design of such devices. In particular, attention will be focused on clear-path indicators, highlighting their role in orientation and mobility tasks. A new device belonging to this class is presented. The detector is based on a multisensor strategy and adopts smart signal processing to provide the user with suitable information about the position of objects hindering his or her path. Experimental trials demonstrate the efficiency of the device developed.
Project Description :
In this project of Multisensor Strategies to Support Blind People: A Clear-Path Indicator we propose a system which can detect obstacles for the blind people. In this new system we increase the range of the operating device to about 40 to 240cm which is possible only through obstacle Sensors. Here We are using ultrasonic sensor for detecting the obstacle. Ultrasonic Receiver is placed in the spectacle. And the transmitter placed in the walking stick. When the obstacle detect the receiver receives the signal from the transmitter. And indicate by voice. Two sensors are placed in the right and left side of the stick. For any obstacle detected we warn the person through Voice Board which gives warning for left and right side.

Block Diagram :
Hardware Used :
Obstacle Sensor.

Signal Processing.

Voice Board.

Power Supply.
Ultrasonic Transmitter & Receiver

Software Used :
Embedded C.
Keil Cross Compiler.
Post: #2

.doc  Multisensor Strategies to Assist Blind People(sameer).doc (Size: 844.5 KB / Downloads: 524)

Multisensor Strategies to Assist Blind People A Clear-Path Indicator

It is a difficult task for the blind people to walk around the road side without any bodyâ„¢s help. This projects demonstrate the Clear path indicator for the blind people which gives them feel comfortable to walk around the road by without anybodyâ„¢s help, by using an embedded device with multiple sensor, which gives an indication to the blind people whenever there is obstacle comes on their way to the walking and this indication will be given with the help of Buzzer sound which gives the audible indication to the blind people.
The stick of the blind people is equipped with multiple sensors and and microcontroller device and gives the buzzer whenever there is an obstacle.
In this project we are going to use LPC2148 (ARM7) based microcontroller, which the current dominant microcontroller in mobile based products and software development Tool as Keil, flash magic for loading hex file in to the microcontroller
SOFTWARE: Embedded ËœCâ„¢
TOOLS: Keil, Flashmagic.
TARGET DEVICE: LPC2148(ARM7) microcontroller.
APPLICATIONS: Clear path indication to the blind people
ADVANTAGES: Low cost and easily solution no need for helper for the blind people. As they can go safely with help of this device
REFERENCE: The 8051 micro controller and embedded systems by Mazidi and LPC datasheets, and the user manual for the LPC2148.
ARM System Developerâ„¢s Guide
-Andrew N.SLOSS
-Domenic Symes
-Chris Wright
1. Introduction to Embedded Systems
2. ARM and Its Architecture
3. LPC2148 Microcontrollers
4. IR Modules & LDR
5. Working flow of the project Block diagram and Schematic diagram
6. Source code
7. Keil software
8. Conclusion
9. Bibiliography
An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions, sometimes with real-time computing constraints. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on programming. Embedded systems have become very important today as they control many of the common devices we use.
Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. Some embedded systems are mass-produced, benefiting from economies of scale.
Physically, embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure.
In general, "embedded system" is not an exactly defined term, as many systems have some element of programmability. For example, Handheld computers share some elements with embedded systems ” such as the operating systems and microprocessors which power them ” but are not truly embedded systems, because they allow different applications to be loaded and peripherals to be connected.
An embedded system is some combination of computer hardware and software, either fixed in capability or programmable, that is specifically designed for a particular kind of application device. Industrial machines, automobiles, medical equipment, cameras, household appliances, airplanes, vending machines, and toys (as well as the more obvious cellular phone and PDA) are among the myriad possible hosts of an embedded system. Embedded systems that are programmable are provided with a programming interface, and embedded systems programming is a specialized occupation.
Certain operating systems or language platforms are tailored for the embedded market, such as Embedded Java and Windows XP Embedded. However, some low-end consumer products use very inexpensive microprocessors and limited storage, with the application and operating system both part of a single program. The program is written permanently into the system's memory in this case, rather than being loaded into RAM (random access memory), as programs on a personal computer are.
We are living in the Embedded World. You are surrounded with many embedded products and your daily life largely depends on the proper functioning of these gadgets. Television, Radio, CD player of your living room, Washing Machine or Microwave Oven in your kitchen, Card readers, Access Controllers, Palm devices of your work space enable you to do many of your tasks very effectively. Apart from all these, many controllers embedded in your car take care of car operations between the bumpers and most of the times you tend to ignore all these controllers.
In recent days, you are showered with variety of information about these embedded controllers in many places. All kinds of magazines and journals regularly dish out details about latest technologies, new devices; fast applications which make you believe that your basic survival is controlled by these embedded products. Now you can agree to the fact that these embedded products have successfully invaded into our world. You must be wondering about these embedded controllers or systems. What is this Embedded System
The computer you use to compose your mails, or create a document or analyze the database is known as the standard desktop computer. These desktop computers are manufactured to serve many purposes and applications.
You need to install the relevant software to get the required processing facility. So, these desktop computers can do many things. In contrast, embedded controllers carryout a specific work for which they are designed. Most of the time, engineers design these embedded controllers with a specific goal in mind. So these controllers cannot be used in any other place.
Theoretically, an embedded controller is a combination of a piece of microprocessor based hardware and the suitable software to undertake a specific task.
These days designers have many choices in microprocessors/microcontrollers. Especially, in 8 bit and 32 bit, the available variety really may overwhelm even an experienced designer. Selecting a right microprocessor may turn out as a most difficult first step and it is getting complicated as new devices continue to pop-up very often.
In the 8 bit segment, the most popular and used architecture is Intel's 8031. Market acceptance of this particular family has driven many semiconductor manufacturers to develop something new based on this particular architecture. Even after 25 years of existence, semiconductor manufacturers still come out with some kind of device using this 8031 core.
Military and aerospace software applications
From in-orbit embedded systems to jumbo jets to vital battlefield networks, designers of mission-critical aerospace and defense systems requiring real-time performance, scalability, and high-availability facilities consistently turn to the LynxOS® RTOS and the LynxOS-178 RTOS for software certification to DO-178B.
Rich in system resources and networking services, LynxOS provides an off-the-shelf software platform with hard real-time response backed by powerful distributed computing (CORBA), high reliability, software certification, and long-term support options.
The LynxOS-178 RTOS for software certification, based on the RTCA DO-178B standard, assists developers in gaining certification for their mission- and safety-critical systems. Real-time systems programmers get a boost with LynuxWorks' DO-178B RTOS training courses.
LynxOS-178 is the first DO-178B and EUROCAE/ED-12B certifiable, POSIX®-compatible RTOS solution.
Communications applications
"Five-nines" availability, CompactPCI hot swap support, and hard real-time response”LynxOS delivers on these key requirements and more for today's carrier-class systems. Scalable kernel configurations, distributed computing capabilities, integrated communications stacks, and fault-management facilities make LynxOS the ideal choice for companies looking for a single operating system for all embedded telecommunications applications”from complex central controllers to simple line/trunk cards.
LynuxWorks Jumpstart for Communications package enables OEMs to rapidly develop mission-critical communications equipment, with pre-integrated, state-of-the-art, data networking and porting software components”including source code for easy customization.
The Lynx Certifiable Stack (LCS) is a secure TCP/IP protocol stack designed especially for applications where standards certification is required.
Electronics applications and consumer devices
As the number of powerful embedded processors in consumer devices continues to rise, the BlueCat® Linux® operating system provides a highly reliable and royalty-free option for systems designers.
And as the wireless appliance revolution rolls on, web-enabled navigation systems, radios, personal communication devices, phones and PDAs all benefit from the cost-effective dependability, proven stability and full product life-cycle support opportunities associated with BlueCat embedded Linux. BlueCat has teamed up with industry leaders to make it easier to build Linux mobile phones with Java integration.
For makers of low-cost consumer electronic devices who wish to integrate the LynxOS real-time operating system into their products, we offer special MSRP-based pricing to reduce royalty fees to a negligible portion of the device's MSRP.
Industrial automation and process control software
Designers of industrial and process control systems know from experience that LynuxWorks operating systems provide the security and reliability that their industrial applications require.
From ISO 9001 certification to fault-tolerance, POSIX conformance, secure partitioning and high availability, we've got it all. Take advantage of our 20 years of experience.
What is the difference between a Microprocessor and Microcontroller By microprocessor is meant the general purpose Microprocessors such as Intel's X86 family (8086, 80286, 80386, 80486, and the Pentium) or Motorola's 680X0 family (68000, 68010, 68020, 68030, 68040, etc). These microprocessors contain no RAM, no ROM, and no I/O ports on the chip itself. For this reason, they are commonly referred to as general-purpose Microprocessors.
A system designer using a general-purpose microprocessor such as the Pentium or the 68040 must add RAM, ROM, I/O ports, and timers externally to make them functional. Although the addition of external RAM, ROM, and I/O ports makes these systems bulkier and much more expensive, they have the advantage of versatility such that the designer can decide on the amount of RAM, ROM and I/O ports needed to fit the task at hand. This is not the case with Microcontrollers.
A Microcontroller has a CPU (a microprocessor) in addition to a fixed amount of RAM, ROM, I/O ports, and a timer all on a single chip. In other words, the processor, the RAM, ROM, I/O ports and the timer are all embedded together on one chip; therefore, the designer cannot add any external memory, I/O ports, or timer to it. The fixed amount of on-chip ROM, RAM, and number of I/O ports in Microcontrollers makes them ideal for many applications in which cost and space are critical.
In many applications, for example a TV remote control, there is no need for the computing power of a 486 or even an 8086 microprocessor. These applications most often require some I/O operations to read signals and turn on and off certain bits.
In the Literature discussing microprocessors, we often see the term Embedded System. Microprocessors and Microcontrollers are widely used in embedded system products. An embedded system product uses a microprocessor (or Microcontroller) to do one task only. A printer is an example of embedded system since the processor inside it performs one task only; namely getting the data and printing it. Contrast this with a Pentium based PC. A PC can be used for any number of applications such as word processor, print-server, bank teller terminal, Video game, network server, or Internet terminal. Software for a variety of applications can be loaded and run. Of course the reason a pc can perform myriad tasks is that it has RAM memory and an operating system that loads the application software into RAM memory and lets the CPU run it.
In an Embedded system, there is only one application software that is typically burned into ROM. An x86 PC contains or is connected to various embedded products such as keyboard, printer, modem, disk controller, sound card, CD-ROM drives, mouse, and so on. Each one of these peripherals has a Microcontroller inside it that performs only one task. For example, inside every mouse there is a Microcontroller to perform the task of finding the mouse position and sending it to the PC. Table 1-1 lists some embedded products.
ARM Architecture & Programming
ARM Architecture & Programming
ARM History
ARM register file & modes of operation
Instruction Set
ARM History
The ARM (Acorn RISC Machine)architecture is developed at Acron Computer Limited of Cambridge, England between 1983-1985. ARM Limited founded in 1990. ARM became as the Advanced RISC Machine is a 32-bit RISC processor architecture that is widely used in embedded designs. ARM cores licensed to semiconductor partners who fabricate and sell to their customers. ARM does not fabricate silicon itself
Because of their power saving features, ARM CPUs are dominant in the mobile electronics market, where low power consumption is a critical design goal. As of 2007, about 98 percent of the more than a billion mobile phones sold each year use at least one ARM CPU.
Today, the ARM family accounts for approximately 75% of all embedded 32-bit RISC CPUs, making it the most widely used 32-bit architecture. ARM CPUs are found in most corners of consumer electronics, from portable devices (PDAs, mobile phones, iPods and other digital media and music players, handheld gaming units, and calculators) to computer peripherals (hard drives, desktop routers).
ARM does not manufacture the CPU itself, but licenses it to other manufacturers to integrate them into their own system
ARM architecture
RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.
History :
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors:
¢ one cycle execution time : RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called ;
¢ pipelining : a techique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions;
¢ large number of registers : the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory
Price/Performance Strategies
Price: move complexity from software to hardware.
Performance: make tradeoffs in favor of decreased code size, at the expense of a higher CPI. Price: move complexity from hardware to software
Performance: make tradeoffs in favor of a lower CPI, at the expense of increased code size.
Design Decisions
¢ Execution of instructions takes many cycles
¢ Design rules are simple thus core operates at higher clock frequencies
¢ Memory-to-memory addressing modes.
¢ A microcode control unit.
¢ Spend fewer transistors on registers. ¢ Simple, single-cycle instructions that perform only basic functions. Assembler instructions correspond to microcode instructions on a CISC machine.
¢ Design rules are more complex and operates at lower clock frequencies
¢ Simple addressing modes that allow only LOAD and STORE to access memory. All operations are register-to-register.
¢ direct execution control unit.
¢ spend more transistors on multiple banks of registers.
¢ use pipelined execution to lower CPI.
Based upon RISC Architecture with enhancements to meet requirements of embedded applications ARM is having
1. A large uniform register file
2. Load-store architecture ,where data processing operations operate on register contents only
3. Uniform and fixed length instructions
4. 32 -bit processor
5. Instructions are 32-bit long
6. Good Speed/Power Consumption Ratio
7. High Code Density
Harvard architecture has separate data and instruction busses, allowing transfers to be performed simultaneously on both busses . Greater amount of instruction parallelism is possible in this architecture. Most DSPs use Harvard architecture for streaming data. The only difference in Harvard architecture to that of Von Neumann architecture is that the program and data memories are separated and use physically separate transmission paths . Enables the machine to transfer instructions and data simultaneously enhances performance. Harvard architecture is more commonly used in specialized microprocessors for real-time and embedded application. However, only the early DSP chips use the Harvard architecture because of the cost. The greatest disadvantage of the Harvard architecture is which needs twice as many address and data pins on the chips
A Von Neumann architecture store program and data in the same memory area with a single bus. So this bus only is used for both data transfers and instruction fetches, and therefore data transfers and instruction fetches must be scheduled - they can not be performed at the same time. Most of the general-purpose microprocessors such as Motorola 68000 and Intel 80x86 use this architecture. It is simple in hardware implementation, but the data and program are required to share a single bus.
ARM Processor Core :
The figure shows the ARM core dataflow model. In which the ARM core as functional units connected by data buses,. And the arrows represent the flow of data, the lines represent the buses, and boxes represent either an operation unit or a storage area. The figure shows not only the flow of data but also the abstract components that make up an ARM core.
Fig : ARM core dataflow model

In the above figure the Data enters the processor core through the Data bus. The data may be an instruction to execute or a data item. This ARM core represents the Von Neumann implementation of the ARM data items and instructions share the same bus. In contrast, Harvard implementations of the ARM use two different buses.
The instruction decoder translates instructions before they are executed. Each instruction executed belongs to a particular instruction set.
The ARM processor ,like all RISC processors, use a load-store architecture. This means it has two instruction types for transferring data in and out of the processor : load instructions copy data from memory to registers in the core, and conversely the store instructions copy data from registers to memory. There are no data processing instructions that directly manipulate data in memory. Thus, data processing is carried out solely in registers.
Data items are placed in the register file “ a storage bank made up of 32-bit registers. Since the ARM core is a 32- bit processor, most instructions treat the registers as holding signed or unsigned 32-bit values.
The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they are read from memory and placed in a register.
The ALU ( arithmetic logic unit ) or MAC ( multiply “ accumulate unit ) takes the register values Rn and Rm from the A and B buses and computes a result. Data processing instructions write the result in Rd directly to the register file. Load and store instructions use the ALU to generate an address to be held in the address register and broadcast on the Address bus.
One important feature of the ARM is that register Rm alternatively can be preprocessed in the barrel shifter before it enters the ALU. Together the barrel shifter and ALU can calculate a wide range of expressions and addresses.
After passing through the functional units, the result in Rd is written back to the register file using the Result bus. For load and store instructions the incrementer updates the address register before the core reads or writes the next register value from or to the next sequential memory location. The processor continues executing instructions until an exception or interrupt changes the normal execution flow.
*ARM Bus Technology :
Embedded systems use different bus technologies. Most common PC bus technology is the Peripheral Component Interconnect ( PCI ) bus. Which connects devices such as video card and disk controllers to the X86 processor bus. This type of technology is called External or Off chip bus technology.
Embedded devices use an on-chip bus that is internal to the chip and allows different peripheral devices to be inter connected with an ARM core.
There are two different types of devices connected to the bus
1. Bus Master
2. Bus Slave
1. Bus Master : A logical device capable of initiating a data transfer with another device across the same bus (ARM processor core is a bus Master ).
2. Bus Slave : A logical device capable only of responding to a transfer request from a bus master device ( Peripherals are bus slaves )
Generally A Bus has two architecture levels
Physical lever : Which covers electrical characteristics an bus width (16,32,64 bus).
Protocol level : which deals with protocol
NOTE :- ARM is primarily a design company . It seldom implements the electrical characteristics of the bus , but it routinely specifies the bus protocol
AMBA (Advanced Microcontroller Bus Architecture )Bus protocol :
AMBA Bus was introduced in 1996 and has been widely adopted as the On Chip bus architecture used for ARM processors.
The first AMBA buses were
1. ARM System Bus ( ASB )
2. ARM Peripheral Bus ( APB )
Later ARM introduced another bus design called the ARM High performance Bus ( AHB )
Using AMBA
i. Peripheral designers can reuse the same design on multiple projects
ii. A Peripheral can simply be bolted on the On Chip bus with out having to redesign an interface for each different processor architecture.
This plug-and-play interface for hardware developers improves availability and time to market.
AHB provides higher data throughput than ASB because it is based on centralized multiplexed bus scheme rather than the ASB bidirectional bus design. This change allows the AHB bus to run at widths of 64 bits and 128 bits
ARM introduced two variations on the AHB bus
1. Multi-layer AHB
2. AHB-Lite
In contrast to the original AHB , which allows a single bus master to be active on the bus at any time , the Multi-layer AHB bus allows multiple active bus masters.
AHB-Lite is a subset of the AHB bus and it is limited to a single bus master. This bus was developed for designs that do not require the full features of the standard AHB bus.
AHB and Multiple-layer AHB support the same protocol for master and slave but have different interconnects. The new interconnects in Multi-layer AHB are good for systems with multiple processors. They permit operations to occur in parallel and allow for higher throughput rates.
Every ARM processor implementation executes a specific instruction set architecture (ISA), although an ISA revision may have more than one processor implementation
The ISA has evolved to keep up with the demands of the embedded market. This evolution has been carefully managed by ARM , so that code written to execute on an earlier architecture revision will also execute on a later revision of the architecture.
The nomenclature identifies individual processors and provides basic information about the feature set.
ARM uses the nomenclature shown below is to describe the processor implementations.The letters and numbers after the word ARM indicate the features a processor may have.
ARM { x }{ y }{ z }{ T }{ D }{ M }{ I }{ E }{J }{ F }{ -S }
x family
y memory management / protection unit
z cache
T Thumb 16 bit decoder
D JTAG debug
M fast multiplier
I EmbeddedICE macrocell
E enhanced instruction ( assumes TDMI )
J Jazelle
F vector floating-point unit
S synthesizible version
All ARM cores after the ARM7TDMI include the TDMI features even though they may not include those letters after the ARM label
The processor family is a group of processor implementations that share the same hardware characteristics. For example, the ARM7TDMI, ARM740T, and ARM720T all share the same family characteristics and belong to the ARM7 family
JTAG is described by IEEE 1149.1 standard Test Access Port and boundary scan architecture. It is a serial protocol used by ARM to send and receive debug information between the processor core and test equipment
EmbeddedICE macrocell is the debug hardware built into the processor that allows breakpoints and watchpoints to be set
Synthesizable means that the processor core is supplied as source code that can be compiled into a form easily used by EDA tools
Introduction to ARM7TDMI core
The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macrocell optimized to provide the best combination of performance, power and area characteristics. The ARM7TDMI core enables system designers to build embedded devices requiring small size, low power and high performance.
ARM7TDMI Features
¢ 32/16-bit RISC architecture (ARM v4T)
¢ 32-bit ARM instruction set for maximum performance and flexibility
¢ 16-bit Thumb instruction set for increased code density
¢ Unified bus interface, 32-bit data bus carries both instructions and data
¢ Three-stage pipeline
¢ 32-bit ALU
¢ Very small die size and low power consumption
¢ Fully static operation
¢ Coprocessor interface
¢ Extensive debug facilities (EmbeddedICE debug unit accessible via JTAG interface unit)
¢ Generic layout can be ported to specific process technologies
¢ Unified memory bus simplifies SoC integration process
¢ ARM and Thumb instructions sets can be mixed with minimal overhead to support application requirements for speed and code density
¢ Code written for ARM7TDMI-S is binary-compatible with other members of the ARM7 Family and forwards compatible with ARM9, ARM9E and ARM10 families, thus it's quite easy to port your design to higher level microcontroller or microprocessor
¢ Static design and lower power consumption are essential for battery -powered devices
¢ Instruction set can be extended for specific requirements using coprocessors
¢ EmbeddedICE-RT and optional ETM units enable extensive, real-time debug facilities
ARM7TDMI Microcontrollers
1. Available ARM7TDMI Microcontrollers
2. Analog Devices ADuC 7xxx
3. Atmel AT91SAM7
4. Freescale MAC7100
5. NXP/Philips LPC2000
6. ST STR710
7.Texas Instruments TMS470
2.3 ARM Register file & modes of operation
Registers : General Purpose registers hold either data or address they are identified with the letter r prefixed to the register number. All registers are of 32 bits.
ARM has 37 registers in total, all of which are 32-bits long.
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
However these are arranged into several banks, with the accessible bank being governed by the processor mode. Each mode can access a particular set of r0-r12 registers, a particular r13 (the stack pointer) and r14 (link register), r15 (the program counter), cpsr (the current program status register)
and privileged modes can also access a particular spsr (saved program status register).
In user mode 16 data registers and 2 status registers are visible. Depending upon context, register r13 and r14 can also be used as General Purpose Registers. In ARM state the registers r0 to r13 are Orthogonal that means - any instruction which use r0 can as well be used with any other General Purpose Register (r1-r13).
The ARM processor has three registers assigned to a particular task or special function: r13,r14 and r15. They are frequently given different labels to differentiate them from the other registers.
Register r13 is traditionally used as the stack pointer (sp) and stores the head of the stack in the current processor mode
Register r14 is called the link register ( lr ) and is where the core puts the return address whenever it calls a subroutine.
Register r15 is the program counter ( pc ) and contains the address of the next instruction to be fetched by the processor
The register file contains all the registers available to a programmer. Which registers are visible to the programmer depend upon the current mode of the processor.
Current program status register :
The ARM core uses the cpsr to monitor and control internal operations. The cpsr is a dedicated 32-bit register and resides in the register file. The following figure shows the generic program status register.
Fig: Program Status Register
The control bit field contains the processor mode, state , and interrupt mask bits (I,F). Reserved bits are allocated for the future versions purpose.
The N, Z, C and V are condition code flags will be changed as a result of arithmetic and logical operations in the processor
N : Negative. Z : Zero. C : Carry. V : Overflow
The I and F bits are the interrupt disable bits
The M0, M1, M2, M3 and M4 bits are the mode bits
Processor Modes: Processor modes determine which register are active, and access rights to CPSR register itself. Each processor mode is either Privileged or Non-privileged. ARM has seven modes. These 7 modes are divided into two types.
Privileged :- Full read-write access to the CPSR. Under this we are having Abort, Fast interrupt request, Interrupt request, Supervisor,System and Undefined
Abort (10111) :
when there is a failed attempt to access memory
Fast interrupt Request (FIQ(10001)) & interrupt request(10010) :
correspond to interrupt levels available on ARM
Supervisor mode(10011) :
state after reset and generally the mode in which OS kernel executes
System mode(11111) :
special version of user mode that allows full read-write access of CPSR
Undefined(11011) :
when processor encounters an undefined instruction
Non-privileged :- Only read access to the control filed of CPSR but read-write access to the condition flags.
User(10000): User mode is user for programs and applications. And this the normal mode
Banked Registers :
Register file contains in all 37 registers. 20 registers are hidden from program at different times. These registers are called banked registers. Banked registers are available only when the processor is in a particular mode. Processor modes (other than system mode) have a set of associated banked registers that are subset of 16 register
Each privileged mode (except system mode) has associated with it a Save Program Status Register, or SPSR. This SPSR is used to save the state of CPSR (Current program status Register) when the privileged mode is entered in order that the user state can be fully restored when the user processor is resumed
Mode Changing :
Mode changes by writing directly to CPSR or by hardware when the processor responds to exception or interrupt
To return to user mode a special return instruction is used that instructs the core to restore the original CPSR and banked registers
ARM Instruction Set
In this chapter we are going to discuss about the most commonly used Instruction Set of ARM. Different ARM architectures revisions support different instructions. However new revisions usually add instructions and remain backwardly compatible. The following shows the type of instructions that ARM support.
I. Data Processing Instructions
II. Branch Instructions
III. Load-store Instructions
IV. Software Interrupt Instruction
V. Program Status Register Instructions
I. Data Processing Instructions :-
The data processing instructions manipulate data within registers. Most data processing instructions can process one of their operands using the barrel shifter. If we use the S suffix on a data processing instruction, then it updates the flags in the cpsr. Move and logical operations update the carry flag C, negative flag N, and Zero flag Z. The carry flag is set from the result of the barrel shift as the last bit shifted out. The N flag is set to bit 31 of the result. The Z flag is set if the result is zero. The following instructions are Data processing instructions.
i). Move instructions: This instruction is used to move the content of one register to another register. The below instructions are the Move instructions
MOV : move a 32-bit value into a register Rd=RS
MOVN : move the NOT of the 32 bit value into a register Rd= ~RS
ii). Barrel Shifter :- A unique and powerful feature of ARM processor is ability to shift the 32-bit binary pattern in one of the source registers left or right by a specific number of positions before it enters the ALU. This is done by using the Barrel shifter. This preprocessing or shift occurs within the cycle time of the instruction. The five different shift operations that we can use within the barrel shifter given below.
LSL : logical shift left
LSR : logical shift right
ASR : arithmetic right shift
ROR : rotate right
RRX : rotate right extended
iii. Arithmetic Instructions : The arithmetic instructions implement and subtraction of 32-bit signed and unsigned values. Some of the instructions of Arithmetic instructions are given below.
ADD :add two 32-bit values.
ADC :add two 32-bit values and carry
SUB :subtract two 32-bit values
SBC : subtract with carry of two 32-bit values
RSB : reverse subtract of two 32-bit values
RSC : reverse subtract with carry of two 32-bit values
iv. Logical Instructions : Performs the logical operations on two source registers
AND : logical bitwise AND of two 32-bit values
ORR : logical bitwise OR of two 32-bit values
EOR : logical exclusive OR of two 32-bit vlaues.
BIC : Logical bit clear (AND NOT)
v. Comparison Instructions : The comparison instructions are used to compare or test a register with a 32 bit value. They update the cpsr flag bits (N, Z, C, V) according to the result, but do not affect other registers. After the bits have been set, the information can then be used to change program flow by using conditional execution. We do not need to apply the S suffix for comparison instructions to update the flag. The following instructions are belong Comparison instructions
CMP (compare) : flags set as a result of R1-R2
CMN (compare negated) : flags set as a result of R1+R2
TST (test for equality of two 32-bit values) : flags set as a result of R1&R2
TEQ (test for equality of two 32-bit values) : flags set as a result of R1^R2
vi. Multiply Instructions : The multiply instructions multiply the content of a pair of registers and , depending upon the instruction, accumulate the results in with another register. The long multiplies accumulate onto a pair of registers representing a 64 bit value. The final result is placed in a destination register or a pair of registers.
MUL : multiply
MLA : multiply and accumulate
Long Multiply Instructions : (Produce 64 bit values,result will be placed in two 32 bit values)
SMLAL : signed multiply accumulate long
SMULL : signed multiply accumulate
UMLAL : unsigned multiply accumulate long
UMULL : unsigned multiply long
II. Branch Instructions :- A branch instruction changes the flow of execution or is used to call a routine. This type of instruction allows programs to have subroutines, if-then-else structures, and loops. The change of execution flow forces the program counter pc to point to new address. The below shown instructions are Branch instructions.
B : branch
BL : branch with link
BX : branch exchange
BLX : branch exchange with link
III. Load-store Instructions :- Load-store instructions transfer data between memory and processor registers.
There are three types of load-store instructions :
i. single register transferring
ii. Multiple register transfer
iii. Swap
Single register transferring :- These instructions are used for moving a single data item in and out of a register. The data types supported are signed and unsigned words(32-bit), halfwords(16-bit), and bytes. The following instructions are various load-store single-register transfer instructions.
LDR : load word into a register
STR : save byte or word from a register
LDRB : load byte into a register
STRB : save byte from a register
LDRH : load halfword into a register
STRH : save halfword into a register
LDRSB : load signed byte into a register
LDRSH : load signed halfword into a register
Multiple register transfer : - Load-store multiple instructions can transfer multiple registers between memory and the processor in a single instruction. The transfer occurs from a base address register Rn pointing into memory. Multiple-register transfer instructions are more efficient from single-register transfers for moving blocks of data around memory and saving and restoring context and stacks. If an interrupt has been raised, then it has no effect until the load-store multiple instruction is complete.
LDM : load multiple registers
STM : save multiple registers
Swap :- The swap instruction is a special case of a load-store instruction. It swaps the contents of memory with the contents of a register. This instruction is an atomic operation- it reads and writes a location in the same bus operation, preventing any other instruction from reading or writing to that location until it completes.
IV. Software Interrupt Instruction :- A software interrupt instruction ( SWI ) causes a software interrupt exception, which provides a mechanism for applications to call operating system routines. The following instruction comes under software interrupt instruction.
SWI : software interrupt
V. Program Status Register Instructions :- The ARM instruction set provides two instructions to directly control a program status ( psr ).
MRS : This instruction transfers the contents of either the cpsr or spsr into a register
MSR : This instruction transfers the content of a register into the cpsr or spsr
Together the above two instructions are used to read and write the cpsr or spsr

General description of LPC 2148:
The LPC2148 microcontrollers is based on a 32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine microcontrollers with embedded high-speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb
mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADCs, 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers suitable for industrial control and medical systems.
General overview of in system programming (ISP):
In-System Programming (ISP) is a process whereby a blank device mounted to a circuit board can be programmed with the end-user code without the need to remove the device from the circuit board. Also, a previously programmed device can be erased and Re programmed without removal from the circuit board. In order to perform ISP operations the microcontroller is powered up in a special ISP mode. ISP mode allows the microcontroller to communicate with an external host device through the serial port, such as a PC or terminal. The microcontroller receives commands and data from the host, erases and reprograms code memory, etc. Once the ISP operations have been completed the device is reconfigured so that it will operate normally the next time it is either reset or power removed and reapplied. All of the Philips microcontrollers shown in Table 1 and Table 2 have a 1 kbyte factory-masked ROM located in the upper 1 kbyte of code memory space from FC00 to FF. This 1 kbyte ROM is in addition to the memory blocks shown in Table 1 and Table 2. This ROM is referred to as the Bootrom. This Bootrom contains a set of instructions which allows the microcontroller to perform a number of Flash programming and erasing functions. The Bootrom also provides communications through the serial port. The use of the Bootrom is key to the concepts of both ISP and In-Application Programming (IAP). The contents of the bootrom are provided by Philips and masked into every device. When the device is reset or power applied, and the EA/ pin is high or at the VPP voltage, the microcontroller will start executing instructions from either the user code memory space at address 0000h (normal mode) or will execute instructions from the Bootrom (ISP mode).
Some applications may have a need to be able to erase and program code memory under the control fo the application. For example, an application may have a need to store calibration information or perhaps need to be able to download new code portions. This ability to erase and program code memory in the end-user application is In-Application Programming (IAP). The Bootrom routines which perform functions on the Flash memory during ISP mode such as programming, erasing, and reading, are also available to end-user programs. Thus it is possible for an end-user application to perform operations on the Flash memory. A common entry point (FFF0h) to these routines has been provided to simplify interfacing to the end-users application. Functions are performed by setting up specific registers as required by a specific operation and performing a call to the common entry point. Like any other subroutine call, after completion of the function, control will return to the end-userâ„¢s code. The Bootrom is shadowed with the user code memory in the address range from FC00h to FFh. This shadowing is controlled by the ENBOOT bit (AUXR1.5). When set, accesses to internal code memory in this address range will be from the boot ROM. When cleared, accesses will be from the userâ„¢s code memory. It will be NECESSARY for the end-userâ„¢s code to set the ENBOOT bit prior to calling the common entry point for IAP operations, even for devices with 16 kbyte, 32 kbyte, and 64 kbyte of internal code memory. (ISP operation is selected by certain hardware conditions and control of the ENBOOT bit is automatic when ISP mode is activated).
Key features:
16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package
8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory; 128-bit wide interface/accelerator enables high-speed 60 MHz operation
In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software, single flash sector or full chip erase in 400 ms and programming of 256 B in 1 ms.
Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip Real Monitor software and high-speed tracing of instruction execution
USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM
In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA
One or two (LPC2141/42 vs, LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog inputs, with conversion times as low as 2.44 ms per channel Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only)
Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog.
Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input
Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities
Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses
Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package
Up to 21 external interrupt pins available
60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 ms
On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz
Power saving modes include Idle and Power-down
Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization
Processor wake-up from Power-down mode via external interrupt or BOD
Single power supply chip with POR and BOD circuits:
CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.

Pin Description:
P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while P0.31 is output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block.

P0.0 ” General purpose input/output digital pin (GPIO)
TXD0 ” Transmitter output for UART0
PWM1 ” Pulse Width Modulator output 1
P0.1 ” General purpose input/output digital pin (GPIO)
RXD0 ” Receiver input for UART0
PWM3 ” Pulse Width Modulator output 3
EINT0 ” External interrupt 0 input
P0.2/SCL0/ CAP0.0:
P0.2 ” General purpose input/output digital pin (GPIO)
SCL0 ” I2C0 clock input/output, open-drain output (for I2C-bus compliance)
CAP0.0 ” Capture input for Timer 0, channel 0
P0.3/SDA0/ MAT0.0/EINT1:
P0.3 ” General purpose input/output digital pin (GPIO)
SDA0 ” I2C0 data input/output, open-drain output (for I2C-bus compliance)
MAT0.0 ” Match output for Timer 0, channel 0
EINT1 ” External interrupt 1 input
P0.4/SCK0/ CAP0.1/AD0.6

P0.4 ” General purpose input/output digital pin (GPIO)
SCK0 ” Serial clock for SPI0, SPI clock output from master or input to slave
CAP0.1 ” Capture input for Timer 0, channel 0
AD0.6 ” ADC 0, input 6.
P0.5/MISO0/ MAT0.1/AD0.7
P0.5 ” General purpose input/output digital pin (GPIO)
MISO0 ” Master In Slave OUT for SPI0, data input to SPI master or data output from
SPI slave.
MAT0.1 ” Match output for Timer 0, channel 1
AD0.7 ” ADC 0, input 7
P0.6/MOSI0/ CAP0.2/AD1.0
P0.6 ” General purpose input/output digital pin (GPIO)
MOSI0 ” Master out Slave In for SPI0, data output from SPI master or data
Input to SPI slave
CAP0.2 ” Capture input for Timer 0, channel 2
AD1.0 ” ADC 1, input 0, available in LPC2144/46/48 only
P0.7 ” General purpose input/output digital pin (GPIO)
SSEL0 ” Slave Select for SPI0, selects the SPI interface as a slave
PWM2 ” Pulse Width Modulator output 2
EINT2 ” External interrupt 2 input
P0.8 ” General purpose input/output digital pin (GPIO)
TXD1 ” Transmitter output for UART1
PWM4 ” Pulse Width Modulator output 4
AD1.1 ” ADC 1, input 1, available in LPC2144/46/48 only
P0.9/RXD1/ PWM6/EINT3:
P0.9 ” General purpose input/output digital pin (GPIO)
RXD1 ” Receiver input for UART1
PWM6 ” Pulse Width Modulator output 6
EINT3 ” External interrupt 3 input
P0.10/RTS1/ CAP1.0/AD1.2:
P0.10 ” General purpose input/output digital pin (GPIO)
RTS1 ” Request to send output for UART1, LPC2144/46/48 only
CAP1.0 ” Capture input for Timer 1, channel 0
AD1.2 ” ADC 1, input 2, available in LPC2144/46/48 only
P0.11/CTS1/ CAP1.1/SCL1:
P0.11 ” General purpose input/output digital pin (GPIO)
CTS1 ” Clear to send input for UART1, available in LPC2144/46/48 only
CAP1.1 ” Capture input for Timer 1, channel 1
SCL1 ” I2C1 clock input/output, open-drain output (for I2C-bus compliance)
P0.12 ” General purpose input/output digital pin (GPIO)
DSR1 ” Data Set Ready input for UART1, available in LPC2144/46/48 only
MAT1.0 ” Match output for Timer 1, channel 0
AD1.3 ” ADC input 3, available in LPC2144/46/48 only
P0.13/DTR1/ MAT1.1/AD1.4:
P0.13 ” General purpose input/output digital pin (GPIO)
DTR1 ” Data Terminal Ready output for UART1, LPC2144/46/48 only
MAT1.1 ” Match output for Timer 1, channel 1
AD1.4 ” ADC input 4, available in LPC2144/46/48 only
P0.14 ” General purpose input/output digital pin (GPIO)
DCD1 ” Data Carrier Detect input for UART1, LPC2144/46/48 only
EINT1 ” External interrupt 1 input
SDA1 ” I2C1 data input/output, open-drain output (for I2C-bus compliance LOW on this pin while RESET is LOW forces on-chip boot loader to take over control of the part after reset
P0.15/RI1/ EINT2/AD1.5:
P0.15 ” General purpose input/output digital pin (GPIO)
RI1 ” Ring Indicator input for UART1, available in LPC2144/46/48 only
EINT2 ” External interrupt 2 input
AD1.5 ” ADC 1, input 5, available in LPC2144/46/48 only
P0.16 ” General purpose input/output digital pin (GPIO)
EINT0 ” External interrupt 0 input
MAT0.2 ” Match output for Timer 0, channel 2
CAP0.2 ” Capture input for Timer 0, channel 2
P0.17/CAP1.2/ SCK1/MAT1.2:
P0.17 ” General purpose input/output digital pin (GPIO)
CAP1.2 ” Capture input for Timer 1, channel 2
SCK1 ” Serial Clock for SSP, clock output from master or input to slave
MAT1.2 ” Match output for Timer 1, channel 2
P0.18 ” General purpose input/output digital pin (GPIO)
CAP1.3 ” Capture input for Timer 1, channel 3
MISO1 ” Master In Slave Out for SSP, data input to SPI master or data output from SSP slave
MAT1.3 ” Match output for Timer 1, channel 3
P0.19 ” General purpose input/output digital pin (GPIO)
MAT1.2 ” Match output for Timer 1, channel 2
MOSI1 ” Master out Slave In for SSP, data output from SSP master or data Input to SSP slave
CAP1.2 ” Capture input for Timer 1, channel 2
P0.20 ” General purpose input/output digital pin (GPIO)
MAT1.3 ” Match output for Timer 1, channel 3
SSEL1 ” Slave Select for SSP, selects the SSP interface as a slave
EINT3 ” External interrupt 3 input
P0.21 ” General purpose input/output digital pin (GPIO)
PWM5 ” Pulse Width Modulator output 5
AD1.6 ” ADC 1, input 6, available in LPC2144/46/48 only
CAP1.3 ” Capture input for Timer 1, channel 3
P0.22 ” General purpose input/output digital pin (GPIO)
AD1.7 ” ADC 1, input 7, available in LPC2144/46/48 only
CAP0.0 ” Capture input for Timer 0, channel 0
MAT0.0 ” Match output for Timer 0, channel 0
P0.23 ” General purpose input/output digital pin (GPIO)
VBUS ” Indicates the presence of USB bus power
This signal must be HIGH for USB reset to occur
P0.25 ” General purpose input/output digital pin (GPIO)
AD0.4 ” ADC 0, input 4
AOUT ” DAC output, available in LPC2142/44/46/48 only
P0.28 ” General purpose input/output digital pin (GPIO)
AD0.1 ” ADC 0, input 1
CAP0.2 ” Capture input for Timer 0, channel 2
MAT0.2 ” Match output for Timer 0, channel 2
P0.29 ” General purpose input/output digital pin (GPIO)
AD0.2 ” ADC 0, input 2
CAP0.3 ” Capture input for Timer 0, Channel 3
MAT0.3 ” Match output for Timer 0, channel 3
P0.30 ” General purpose input/output digital pin (GPIO)
AD0.3 ” ADC 0, input 3
EINT3 ” External interrupt 3 input
CAP0.0 ” Capture input for Timer 0, channel 0
P0.31 ” General purpose output only digital pin (GPO)
UP_LED ” USB Good Link LED indicator, it is LOW when device is configured (non-control endpoints enabled), it is HIGH when the device is not configured or during global suspend
CONNECT ” Signal used to switch an external 1.5 kohms resistor under the
Software control, used with the Soft Connect USB feature
Important: This is a digital output only pin, this pin MUST NOT be externally pulled LOW when RESET pin is LOW or the JTAG port will be disabled P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit, the operation of port 1 pins depends upon the pin function selected via the pin connect block, pins 0 through 15 of port 1 are not
P1.16 ” General purpose input/output digital pin (GPIO)
TRACEPKT0 ” Trace Packet, bit 0, standard I/O port with internal pull-up
P1.17 ” General purpose input/output digital pin (GPIO)
TRACEPKT1 ” Trace Packet, bit 1, standard I/O port with internal pull-up
P1.18 ” General purpose input/output digital pin (GPIO)
TRACEPKT2 ” Trace Packet, bit 2, standard I/O port with internal pull-up
P1.19 ” General purpose input/output digital pin (GPIO)
TRACEPKT3 ” Trace Packet, bit 3, standard I/O port with internal pull-up
P1.20 ” General purpose input/output digital pin (GPIO)
TRACESYNC ” Trace Synchronization, standard I/O port with internal pull-up
Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to operate as Trace port after reset
P1.21 ” General purpose input/output digital pin (GPIO)
PIPESTAT0 ” Pipeline Status, bit 0, standard I/O port with internal pull-up
P1.22 ” General purpose input/output digital pin (GPIO)
PIPESTAT1 ” Pipeline Status, bit 1, standard I/O port with internal pull-up
P1.23 ” General purpose input/output digital pin (GPIO)
PIPESTAT2 ” Pipeline Status, bit 2, standard I/O port with internal pull-up
P1.24 ” General purpose input/output digital pin (GPIO)
TRACECLK ” Trace Clock, standard I/O port with internal pull-up
P1.25 ” General purpose input/output digital pin (GPIO)
EXTIN0 ” External Trigger Input, standard I/O with internal pull-up
P1.26 ” General purpose input/output digital pin (GPIO)
RTCK ” Returned Test Clock output, extra signal added to the JTAG port, assists debugger synchronization when processor frequency varies, bidirectional pin with internal pull-up
Note: LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate a Debug port after reset
P1.27 ” General purpose input/output digital pin (GPIO)
TDO ” Test Data out for JTAG interface
P1.28 ” General purpose input/output digital pin (GPIO)
TDI ” Test Data in for JTAG interface
P1.29 ” General purpose input/output digital pin (GPIO)
TCK ” Test Clock for JTAG interface
P1.30 ” General purpose input/output digital pin (GPIO)
TMS ” Test Mode Select for JTAG interface
P1.31 ” General purpose input/output digital pin (GPIO)
TRST ” Test Reset for JTAG interface
D+: USB bidirectional D+ line
D- : USB bidirectional D- line
RESET External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0, TTL with hysteretic, 5 V tolerant
XTAL1: Input to the oscillator circuit and internal clock generator circuits
XTAL2: Output from the oscillator amplifier
RTCX1: I Input to the RTC oscillator circuit
RTCX2: Output from the RTC oscillator circuit
VSS: 6, 18, 25, 42, 50 pins are for supply voltage.
Ground: 0 V reference.
VSSA Analog ground: 0 V reference, this should nominally be the same voltage as
VSS, but should be isolated to minimize noise and error
VDD 23, 43, 51 I 3.3 V power supply: This is the power supply voltage for the core and I/O ports.
VDDA 7 I Analog 3.3 V power supply: This should be nominally the same voltage as
VDD but should be isolated to minimize noise and error, this voltage is only used to power the on-chip ADC(s) and DAC
VREF ADC reference voltage: This should be nominally less than or equal to the
VDD voltage but should be isolated to minimize noise and error, level on this
Pin is used as a reference for ADC(s) and DAC
VBAT RTC power supply voltage: 3.3 V on this pin supplies the power to the RTC.
Functional Description:
Architectural Overview:
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
And impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set.
Essentially, the ARM7TDMI-S processor has two instruction sets:
¢ The standard 32-bit ARM set
¢ A 16-bit Thumb set
The Thumb setâ„¢s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMâ„¢s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections (such as interrupt service routines and DSP algorithms) in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30 % over Thumb mode.
On-Chip Flash Program memory:
The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. Due to the architectural solution chosen for an on-chip boot loader, flash memory available for userâ„¢s code on LPC2141/42/44/46/48 is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively.
The LPC2141/42/44/46/48 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data-retention.
On-Chip Static RAM:
On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB, 16 kB and 32 kB of static RAM respectively. In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution.
Memory Map
The LPC2141/42/44/46/48 memory map incorporates several distinct regions, as shown below.
Interrupt controller:
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.
Fast interrupt request (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.
Interrupt Sources:
Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
Pin Connect Block:
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.
The Pin Control Module with its pin select registers defines the functionality of the microcontroller in a given hardware environment. After reset all pins of Port 0 and Port 1 are configured as input with the following exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality; if trace is enabled, the Trace pins will assume their trace functionality. The pins associated with the I2C0 and I2C1 interface are open drain.
Fast General purpose Parallel I/O:
Device pins that are not connected to a specific
Post: #3

.docx  Multisensor Strategies to Support Blind People-A Clear-Path Indicator.docx (Size: 2.22 MB / Downloads: 314)


In this project of Multisensor Strategies to Support Blind People: A Clear-Path Indicator we propose a system which can detect obstacles for the blind people. In this new system we increase the range of the operating device to about 40 to 240cm which is possible only through obstacle Sensors. Here we are using ultrasonic sensor for detecting the obstacle. Ultrasonic Receiver is placed in the spectacle. And the transmitter placed in the walking stick. When the obstacle detect the receiver receives the signal from the transmitter. And indicate by voice. Two sensors are placed in the right and left side of the stick. For any obstacle detected we warn the person through Voice Board which gives warning for left and right side.

In this project we trying to define the criteria required for the development for the sensing devices. Now we are presenting a kit which is prototype of this sensing device.
For this project we are using Rabbit processor, ultra sonic sensors, voice recorder and 8 ohms speaker.






The Rabbit 3000 is a modern 8-bit microprocessor that is the central element of a complete and fully supported embedded design system that includes development tools, software libraries, core modules, sample designs, a parts store, and readily available expert, human support. This Development Kit has the essentials that you need to design your own microprocessor-based system, and includes a complete Dynamic C software development system. This Development Kit contains a powerful Rabbit Core module (the RCM3110) and Prototyping Board that will allow you to evaluate the Rabbit 3000 and to prototype circuits that interfaces to a Rabbit 3000 microprocessor. You will also be able to write and test software for the RCM3100 series Rabbit Core modules. The Rabbit 3000 has an extensive array of on-chip peripherals including 6 serial ports, 56 parallel I/O pins, motion control interfaces, a time/date clock, glue less memory and I/O interfacing, a slave interface, and in-circuit programming.
The RCM3100 Rabbit Core microprocessor core module is the ideal option for designers who want to rapidly develop and implement embedded systems. Powered by the new Rabbit® 3000 microprocessor, the compact RCM3100 boasts powerful features and a small footprint“1.85" × 1.65" (47 × 42 mm)“to simplify integration.
The RCM3100 has 6 serial ports and operates at 29.4 MHz and 3.3 V (with 5 V-tolerant I/O). Built-in low-EMI features, including a clock spectrum spreader, help designers eliminate the kind of emissions-related problems that frequently derail tight development schedules.
Available in two models, the RCM3100 is equipped with up to 512K each of Flash and SRAM, quadrature encoder inputs, PWM outputs, and pulse capture and measurement capabilities. Two 34-pin connection headers provide 54 digital I/O shared with the 6 serial ports and alternate I/O features. The RCM3100 features a battery-back able real-time clock, glue less memory and I/O interfacing, and low power "sleepy" modes (<2mA). A fully enabled 8-bit slave port permits easy master-slave interfacing with another processor-based system, and an alternate I/O bus can be configured for 8 data lines and 6 address lines (shared with parallel I/O). The Rabbit 3000 processor's compact, C-friendly instruction set and high clock speeds produce exceptionally fast results for math, logic, and I/O.

4.1.2 RCM3100 Features

¢ Small size: 1.65" x 1.85" x 0.55"
(42 mm × 47 mm × 14 mm)
¢ Microprocessor: Rabbit 3000 running at 29.4 MHz
¢ 54 parallel 5 V tolerant I/O lines: 46 configurable for I/O, 4 fixed inputs, 4 fixed outputs
¢ Two additional digital inputs, two additional digital outputs
¢ External reset input
¢ Alternate I/O bus can be configured for 8 data lines and 6 address lines (shared with
Parallel I/O lines), I/O read/write
¢ Ten 8-bit timers (six cascadable) and one 10-bit timer with two match registers
¢ 256K“512 K flash memories, 128K“512K SRAM
¢ Real-time clock
¢ Watchdog supervisor
¢ Provision for customer-supplied backup battery via connections on header J2
¢ 10-bit free-running PWM counter and four pulse-width registers
¢ Two-channel Input Capture can be used to time input signals from various port pins
¢ Two-channel Quadrature Decoder accepts inputs from external incremental encoder
¢ Six CMOS-compatible serial ports: maximum asynchronous baud rate of 3.68 Mbps,
Maximum synchronous baud rate of 7.35 Mbps. Four ports are configurable as a
Clocked serial port (SPI), and two ports are configurable as SDLC/HDLC serial ports.
¢ Supports 1.15 Mbps IrDA transceiver
Appendix A, Rabbit Core RCM3100 Specifications, provides detailed specifications for
The RCM3100.
Two different RCM3100 models are available. In addition, the RCM3100 Series Rabbit-
Core modules provide Ethernet connectivity.

4.1.2 Advantages of the RCM3100

¢ Fast time to market using a fully engineered, ready to run microprocessor core.
¢ Competitive pricing when compared with the alternative of purchasing and assembling
Individual components.
¢ Easy C-language program development and debugging
¢ Utility programs for rapid production loading of programs.
¢ Generous memory size allows large programs with tens of thousands of lines of code,
And substantial data storage.
RCM3100 Series Rabbit Core Modules
The RCM3100 series Rabbit Core modules are designed for use on a customer-supplied
Mother board that supplies power and interfaces to real-world I/O devices. Their two 34-
Pin connection headers provide 54 digital parallel user I/O lines, shared with five serial
ports, along with control lines. A sixth serial port and one additional I/O line are available
on the programming header.
A fully enabled slave port permits glue less master-slave interface with another Rabbit based
system. The slave port may also be used with non-Rabbit systems, although additional
logic may be required.
The RCM3100 series is equipped with 256K“512K flash memory and 128K“512K static
There are two production models in the RCM3100 series. If the standard models do not
serve your needs, other variations can be specified and ordered in production quantities.
Contact your Z-World or Rabbit Semiconductor sales representative for details.
Table 1 below highlights the differences between the two models in the RCM3100 family.
In addition, there is an RCM3000 series of Rabbit Core modules that includes Ethernet connectivity.
The Rabbit Core modules can be programmed locally, remotely, or via a network using
appropriate interface hardware.
The RCM3100 modules have two 34-pin headers to which cables can be connected, or
which can be plugged into matching sockets on a production device. The pin outs for these
connectors are shown in Figure 1 below.


Headers J1 and J2 are standard 2 × 34 headers with a nominal 2 mm pitch.
The signals labeled PD0“PD3, PD6, and PD7 on header J1 (pins 29“34) and the pin that is
not connected (pin 33 on header J2) are reserved for future use on other Rabbit Core modules.
The Prototyping Board is actually both a demonstration board and a prototyping board.
As a demonstration board, it can be used to demonstrate the functionality of the RCM3100
right out of the box without any modifications to either board. There are no jumpers or dip
switches to configure or misconfigure on the Prototyping Board so that the initial setup is
very straightforward.
The Prototyping Board comes with the basic components necessary to demonstrate the
operation of the RCM3100. Two LEDs (DS1 and DS2) are connected to PG6 and PG7,
and two switches (S2 and S3) are connected to PG1 and PG0 to demonstrate the interface
to the Rabbit 3000 microprocessor. Reset switch S1 is the hardware reset for the
The Prototyping Board provides the user with RCM3100 connection points brought out conveniently to labeled points at headers J2 and J4 on the Prototyping Board. Small to medium circuits can be prototyped using point-to-point wiring with 20 to 30 AWG wire between the
prototyping area and the holes at locations J2 and J4. The holes are spaced at 0.1" (2.5 mm),
and 40-pin headers or sockets may be installed at J2 and J4. The pinouts for locations J2 and
J4, which correspond to headers J1 and J2



The ports on the Rabbit 3000 microprocessor used in the RCM3100 Series are configurable,
and so the factory defaults can be reconfigured. Table 1 lists the Rabbit 3000 factory
defaults and the alternate configurations.


This chapter describes the RCM3100 hardware in more detail, and explains how to set up and use the accompanying Prototyping Board.
NOTE: These chapters (and this manual) assume that you have the RCM3100 Development Kit. If you purchased an RCM3100 module by itself, you will have to adapt the information in this chapter and elsewhere to your test and development setup. DEVELOPMENT KIT CONTENTS:

The RCM3100 Development Kit contains the following items:
¢ RCM3110 module, 256K flash memory, and 128K SRAM.
¢ RCM3000/RCM3100 Prototyping Board.
¢ AC adapter, 9 V DC, 1 A. (Included only with Development Kits sold for the North
American market. A header plug leading to bare leads is provided to allow overseas
Users to connect a power supply compatible with their local mains power.)
¢ 10-pin header to DE9 programming cable with integrated level-matching circuitry.
¢ Dynamic C CD-ROM, with complete product documentation on disk.
¢ This Getting started manual.
¢ A bag of accessory parts for use on the Prototyping Board.
¢ Registration card. PROTOTYPING BOARD

The Prototyping Board included in the Development Kit makes it easy to connect an
RCM3100 series module to a power supply and a PC workstation for development. It also
Provides some basic I/O peripherals (switches and LEDs), as well as a prototyping area for
More advanced hardware development. For the most basic level of evaluation and development, the Prototyping Board can be used without modification. As you progress to more sophisticated experimentation and hardware development, modifications and additions can be made to the board without modifying or damaging the RCM3100 module itself. The Prototyping Board is shown below in Figure 2, with its main features identified.

Prototyping Board Features

¢ Power Connection”A power-supply jack and a 3-pin header are provided for connection
to the power supply. Note that the 3-pin header is symmetrical, with both outer
pins connected to ground and the center pin connected to the raw V+ input. The cable
of the AC adapter provided with the North American version of the Development Kit
Ends in a plug that connects to the power-supply jack. The header plug leading to bare
Leads provided for overseas customers can be connected to the 3-pin header in either
Orientation. Users providing their own power supply should ensure that it delivers 8“24 V DC at
1 A. The voltage regulators will get warm while in use.
¢ Regulated Power Supply”The raw DC voltage provided at the POWER IN jack is
routed to a 5 V switching voltage regulator, then to a separate 3.3 V linear regulator.
The regulators provide stable power to the RCM3100 series module and the Prototyping
¢ Power LED”The power LED lights whenever power is connected to the Prototyping
¢ Reset Switch”A momentary-contact, normally open switch is connected directly to the
RCM3100â„¢s /RESET_IN pin. Pressing the switch forces a hardware reset of the system.
¢ I/O Switches and LEDs”Two momentary-contact, normally open switches are connected
to the PG0 and PG1 pins of the master RCM3100 module and may be read as
inputs by sample applications.
Two LEDs are connected to the PG6 and PG7 pins of the master module, and may be
driven as output indicators by sample applications.
¢ Prototyping Area”A generous prototyping area has been provided for the installation
of through-hole components. +3.3 V, +5 V, and Ground buses run around the edge of
this area. Several areas for surface-mount devices are also available. (Note that there
are SMT device pads on both top and bottom of the Prototyping Board.) Each SMT pad
is connected to a hole designed to accept a 30 AWG solid wire.
¢ Slave Module Connectors”A second set of connectors is pre-wired to permit installation
of a second, slave RCM3100 series or RCM3100 series module. This capability
is reserved for future use, although the schematics in this manual contain all of the
details an experienced developer will need to implement a master-slave system.
¢ Module Extension Headers”The complete pin sets of both the MASTER and
SLAVE RabbitCore modules are duplicated at these two sets of headers. Developers
can solder wires directly into the appropriate holes, or, for more flexible development,
26-pin header strips can be soldered into place. See Figure 1 for the header pinouts.
¢ RS-232”Two 3-wire or one 5-wire RS-232 serial port are available on the Prototyping
Board. Refer to the Prototyping Board schematic (090-0137) for additional details.
A 10-pin 0.1-inch spacing header strip is installed at J5 to permit connection of a ribbon
cable leading to a standard DE-9 serial connector.
¢ Current Measurement Option”Jumpers across pins 1“2 and 5“6 on header JP1 can
be removed and replaced with an ammeter across the pins to measure the current drawn
from the +5 V or the +3.3 V supplies, respectively.
¢ Motor Encoder”A motor/encoder header is provided at header J6 for future use.
¢ LCD/Keypad Module”Z-World™s LCD/keypad module (Z-World part number
101-0465) may be plugged in directly to headers J7, J8, and J10. DEVELOPMENT HARDWARE CONNECTIONS
There are four steps to connecting the Prototyping Board for use with Dynamic C and the
sample programs:
1. Attach the RCM3100 series module to the Prototyping Board.
2. Connect the programming cable between the RCM3100 module and the workstation PC.
3. Connect the power supply to the Prototyping Board. ATTACH MODULE TO PROTOTYPING BOARD
Turn the RCM3100 series module so that the mounting holes on the RCM3100 and on the
Prototyping Board line up, as shown in Figure 3 below. Align the module headers J1 and
J2 into sockets J12 and J13 on the Prototyping Board.
Although you can install a single module into either the MASTER or the SLAVE position on the Prototyping Board, all the Prototyping Board features (switches, LEDs, serial port drivers, etc.) are connected to the MASTER position. We recommend you install the RCM3100 module in the MASTER position unless you plan to use it as a slave with another RCM3000 or RCM3100 series board. CONNECT PROGRAMMING CABLE

The programming cable connects the Rabbit Core module to the PC running Dynamic C to
download programs and to monitor the Rabbit Core module for debugging. Connect the 10-pin connector of the programming cable labeled PROG to header J1 on the RCM3100 series module as shown in Figure 4. Be sure to orient the marked (usually red) edge of the cable towards pin 1 of the connector. (Do not use the DIAG connector, which is used for a normal serial connection.)
When all other connections have been made, you can connect power to the RCM3000/RCM3100 Prototyping Board.

4.1.5 MEMORY

The RCM3100 is designed to accept 128K to 512K of SRAM packaged in a 32-pin TSOP
or sTSOP case.
The RCM3100 is also designed to accept 256K to 512K of flash EPROM packaged in a
32-pin TSOP or sTSOP case.
NOTE: Z-World recommends that any customer applications should not be constrained
by the sector size of the flash EPROM since it may be necessary to change the sector
size in the future. Memory I/O Interface
The Rabbit 3000 address lines (A0“A19) and all the data lines (D0“D7) are routed internally
to the onboard flash memory and SRAM chips. I/0 write (/IOWR) and I/0 read
(/IORD) are available for interfacing to external devices.
Parallel Port A can also be used as an external I/O data bus to isolate external I/O from the
main data bus. Parallel Port B pins PB3“PB7 can also be used as an external address bus.
When using the auxiliary I/O bus instead of the default address bus, you must add the following
line at the beginning of your program.
#define PORTA_AUX_IO // required to enable auxiliary I/O bus
The STATUS output has three different programmable functions:
1. It can be driven low on the first op code fetch cycle.
2. It can be driven low during an interrupt acknowledge cycle.
3. It can also serve as a general-purpose output.

I/O Buffer Sourcing and Sinking Limit

Unless otherwise specified, the Rabbit 3000 I/O buffers are capable of sourcing and sinking 6.8 mA of current per pin at full AC switching speed. Full AC switching assumes a
29.4 MHz CPU clock and capacitive loading on address and data lines of less than 70 pF
Per pin. The maximum Vcc is 3.6 V, and the absolute maximum operating voltage on all
Parallel I/O is 5.5 V.
Table A-6 shows the AC and DC output drive limits of the parallel I/O buffers when the
Rabbit 3000 is used in the RCM3100.
Under certain conditions, the maximum instantaneous AC/DC sourcing or sinking current
may be greater than the limits outlined in Table A-6. The maximum AC/DC sourcing current
can be as high as 12.5 mA per buffer as long as the number of sourcing buffers does
not exceed three per VDD or VSS pad, or up to six outputs between pads. Similarly, the
maximum AC/DC sinking current can be as high as 8.5 mA per buffer as long as the number
of sinking buffers does not exceed three per VDD or VSS pad, or up to six outputs
between pads. The VDD bus can handle up to 35 mA, and the VSS bus can handle up to
28 mA. All these analyses were measured at 100°C.

4.1.6 Serial Communication

The RCM3100 Series board does not have an RS-232 or an RS-485 transceiver directly on
the board. However, an RS-232 or RS-485 interface may be incorporated on the board the
RCM3100 is mounted on. For example, the Prototyping Board has a standard RS-232
transceiver chip. Serial Ports

There are six serial ports designated as Serial Ports A, B, C, D, E, and F. All six serial
ports can operate in an asynchronous mode up to the baud rate of the system clock divided
by 16. An asynchronous port can handle 7 or 8 data bits. A 9th bit address scheme, where
an additional bit is sent to mark the first byte of a message, is also supported. Serial Ports
A, B, C, and D can also be operated in the clocked serial mode. In this mode, a clock line
synchronously clocks the data in or out. Either of the two communicating devices can supply
the clock. When the Rabbit 3000 provides the clock, the baud rate can be up to 80% of
the system clock frequency divided by 128, or 183,750 bps for a 29.4 MHz clock speed.
Serial Ports E and F can also be configured as SDLC/HDLC serial ports. The IRDA protocol
is also supported in SDLC format by these two ports. Serial Port A is available only on the programming port, and so is likely to be inconvenient
to interface with. PROGRAMMING PORTS

Serial Port A has special features that allow it to cold-boot the system after reset. Serial
Port A is also the port that is used for software development under Dynamic C.
The Rabbit Core RCM3100 Series has a 10-pin program header labeled J3. The Rabbit
3000 startup-mode pins (SMODE0, SMODE1) are presented to the programming port so
that an externally connected device can force the RCM3100 to start up in an external bootstrap
mode. The Rabbit 3000 Microprocessor Userâ„¢s Manual provides more information
related to the bootstrap mode. The programming port is used to start the Rabbit Core RCM3100 in a mode where it will download a program from the port and then execute the program. The programming port transmits information to and from a PC while a program is being debugged in-circuit. The Rabbit Core RCM3100 can be reset from the programming port via the /RESET_IN line. The Rabbit 3000 status pin is also presented to the programming port. The status pin is an
output that can be used to send a general digital signal. The clock line for Serial Port A is presented to the programming port, which makes synchronous serial communication possible.
Alternate Uses of the Programming Port
The programming port may also be used as an application port with the DIAG connector
on the programming cable.
All three clocked Serial Port A signals are available as
¢ a synchronous serial port
¢ an asynchronous serial port, with the clock line usable as a general CMOS input
¢ two general CMOS inputs and one general CMOS output.
Two startup mode pins, SMODE0 and SMODE1, are available as general CMOS inputs
after they are read during the initial boot-up. The logic state of these two pins is very
important in determining the startup procedure after a reset.
/RES_IN is an external input used to reset the Rabbit 3000 microprocessor.
The status pin may also be used as a general CMOS output.
See Appendix E, Programming Cable, for more information.

4.1.7 Other Hardware Clock Doubler
The RCM3100 takes advantage of the Rabbit 3000 microprocessorâ„¢s internal clock doubler.
A built-in clock doubler allows half-frequency crystals to be used to reduce radiated
Emissions. The 29.4 MHz frequency specified for the RCM3100 is generated using a
14.7456 MHz crystal.
The clock doubler may be disabled if 29.4 MHz clock speeds are not required. Disabling
the Rabbit 3000 microprocessorâ„¢s internal clock doubler will reduce power consumption
and further reduce radiated emissions. The clock doubler is disabled with a simple change
to the BIOS as described below. Spectrum Spreader
The Rabbit 3000 features a spectrum spreader, which helps to mitigate EMI problems. By
default, the spectrum spreader is on automatically, but it may also be turned off or set to a
stronger setting. The means for doing so is through a simple change to the following BIOS
line in a way that is similar to the clock doubler described above.
#define ENABLE_SPREADER 1 // Set to 0 to disable spectrum spreader,
// 1 to enable normal spreading, or
// 2 to enable strong spreading.
NOTE: The strong spectrum-spreading setting is not recommended since it may limit the
maximum clock speed or the maximum baud rate.
1. Open the BIOS source code file, RABBITBIOS.C in the BIOS directory.
2. Change the line
#define CLOCK_DOUBLED 1 // set to 1 to double clock if
// Rabbit 2000: crystal <= 12.9024 MHz,
// Rabbit 3000: crystal <= 26.4192 MHz,
// or to 0 to always disable clock doubler
to read as follows.
3. Save the change using File > Save.

4.1.8 Other Inputs and Outputs

Two status mode pins, SMODE0 and SMODE1, are available as inputs. The logic state of these two pins determines the startup procedure after a reset. /RESET_IN is an external input used to reset the Rabbit 3000 microprocessor and the RabbitCore RCM3100 memory. /RES is an output from the reset circuitry that can be used to reset other peripheral devices.

4.1.9 5 V Tolerant Inputs

The RCM3100 operates over a voltage from 3.15 V to 3.45 V, but most RCM3100 input
pins, except /RESET_IN, VRAM, VBAT_EXT, and the power-supply pins, are 5 V tolerant.
When a 5 V signal is applied to 5 V tolerant pins, they present a high impedance even if
the Rabbit power is off. The 5 V tolerant feature allows 5 V devices that have a suitable
switching threshold to be connected directly to the RCM3100. This includes HCT family
parts operated at 5 V that have an input threshold between 0.8 and 2 V.
NOTE: CMOS devices operated at 5 V that have a threshold at 2.5 V are not suitable for
direct connection because the Rabbit 3000 outputs do not rise above VDD, and is often
specified as 3.3 V. Although a CMOS input with a 2.5 V threshold may switch at 3.3 V,
it will consume excessive current and switch slowly.
In order to translate between 5 V and 3.3 V, HCT family parts powered from 5 V can be
used, and are often the best solution. There is also the LVT family of parts that operate
from 2.0 V to 3.3 V, but that have 5 V tolerant inputs and are available from many suppliers.
True level-translating parts are available with separate 3.3 V and 5 V supply pins, but
these parts are not usually needed, and have design traps involving power sequencing.




The RCM3100 requires a regulated 3.3 V ± 0.15 V DC power source to operate. Depending on the amount of current required by the application, different regulators can be used
To supply this voltage.
The AC adapter supplied with the RCM3100 Development Kit provides 9 V at up to 1 A
As the input to the voltage regulator on the Prototyping Board. The Prototyping Board has
An onboard +5 V switching power regulator from which a +3.3 V linear regulator draws
Its supply. Thus both +5 V and +3.3 V are available on the Prototyping Board.
The Prototyping Board itself is protected against reverse polarity by a Shottky diode at D2
As shown in Figure B-2.


The RCM3100 does not have a battery, but there is provision for a customer-supplied battery
to back up SRAM and keep the internal Rabbit 3000 real-time clock running.
Header J2, shown in Figure D-1, allows access to the external battery. This header makes
it possible to connect an external 3 V power supply. This allows the SRAM and the internal
Rabbit 3000 real-time clock to retain data with the RCM3100 powered down.
A lithium battery with a nominal voltage of 3 V and a minimum capacity of 165 mA¢h is
recommended. A lithium battery is strongly recommended because of its nearly constant
nominal voltage over most of its life.
The drain on the battery by the RCM3100 is typically 7.1 μA when no other power is supplied. If a 165 mA¢h battery is used, the battery can last almost 3 years:
The actual life in your application will depend on the current drawn by components not on
the RCM3100 and the storage capacity of the battery. Note that higher capacity lithium ion
batteries are available and that the shelf life of a lithium ion battery is ultimately 10 years.
The RCM3100 does not drain the battery while it is powered up normally.


4.2.1 General Description:

This circuit offers true single-chip voice recording, non volatile storage, and Playback capability for 40 to 60 seconds. It supports both random and sequential access of multiple messages. It can be used in three different modes. The APR96 00 device offers true single-chip voice recording, non-volatile storage, and playback capability for 40 to 60 seconds. The device supports both random and sequential access of multiple messages. Sample rates are user-selectable, allowing designers to customize their design for unique quality and storage time needs. Integrated output amplifier, microphone amplifier, and AGC circuits greatly simplify system design. the device is ideal for use in portable voice recorders, toys, and many other consumer and industrial applications.
APLUS integrated achieves these high levels of storage capability by using its proprietary analog/multilevel storage technology implemented in an advanced Flash non-volatile memory process, where each memory cell can store 256 voltage levels. This technology enables the APR9600 device to reproduce voice signals in their natural form. It eliminates the need for encoding and compression, which often introduce distortion.
APR9600 is a low-cost high performance sound record/replay IC incorporating flash analogue storage technique. Recorded sound is retained even after power supply is removed from the module. The replayed sound exhibits high quality with a low noise level. Sampling rate for a 60 second recording period is 4.2 kHz that gives a sound record/replay bandwidth of 20Hz to 2.1 kHz. However, by changing an oscillation resistor, a sampling rate as high as 8.0 kHz can be achieved. This shortens the total length of sound recording to 32 seconds. Total sound recording time can be varied from 32 seconds to 60 seconds by changing the value of a single resistor. The IC can operate in one of two modes: serial mode and parallel mode.
In serial access mode, sound can be recorded in 256 sections. In parallel access mode, sound can be recorded in 2, 4 or 8 sections. The IC can be controlled simply using push button keys. It is also possible to control the IC using external digital circuitry such as micro-controllers and computers.
The APR9600 has a 28 pin DIP package. Supply voltage is between 4.5V to 6.5V. During recording and replaying, current consumption is 25 mA. In idle mode, the current drops to 1 A. The APR9600 experimental board is an assembled PCB board consisting of an APR9600 IC, an electrets microphone, support components and necessary switches to allow users to explore all functions of the APR9600 chip. The oscillation resistor is chosen so that the total recording period is 60 seconds with a sampling rate of 4.2 kHz. The board measures 80mm by 55mm.


¢ Single-chip, high-quality voice recording & playback solution
- No external ICs required
- Minimum external components
¢ Non-volatile Flash memory technology
- No battery backup required
¢ User-Selectable messaging options
- Random access of multiple fixed-duration messages
- Sequential access of multiple variable-duration messages
¢ User-friendly, easy-to-use operation
- Programming & development systems not required
- Level-activated recording & edge-activated play back switches
¢ Low power consumption
- Operating current: 25 mA typical
- Standby current: 1 uA typical
- Automatic power-down
¢ Chip Enable pin for simple message expansion


On power up , the device is ready to record or playback. To record, the chip enable pin, Pin no 23 has to be set low to enable the device and there is a slide switch which is connected to pin no 27 must be set low to enable the Recording. To initiate the recording apply the low signal on the message trigger pins. The message trigger pin is M1, M2, M3, M4, M5, M6, M7, M8. Recording continues as long as the message trigger pin is kept LOW. Actual recording begins, & the device responds with a single beep at the speaker output, to indicate that it has started recording. Busy Indicator LED (CONNECTED AT PIN NO 10) glows till the message trigger pin is kept low. Also the LED connected at strobe pin flashes while recording. A beep is heard when message trigger pin is made high (indicates message recording is over), & both the LEDS goes off. Two beeps are heard as an indication of memory overflow of current recording segment.



APR9600 block diagram is included in order to describe the device's internal Architecture. At the left hand side of the diagram are the analog inputs. A differential microphone amplifier, including integrated AGC, is included on-chip for applications requiring use. The amplified microphone signals fed into the device by connecting the ANA_OUT pin to the ANA_IN pin through an external DC blocking capacitor. Recording can be fed directly into the ANA_IN pin through a DC blocking capacitor, however, the connection between ANA_IN and ANA_OUT is still required for playback. The next block encountered by the input signal is the internal anti-aliasing filter. The filter automatically adjusts its response according to the sampling frequency selected so Shannonâ„¢s Sampling Theorem is satisfied. After anti-aliasing filtering is accomplished the signal is ready to be clocked into the memory array. This storage is accomplished through a combination of the Sample and Hold circuit and the Analog Write/Read circuit. These circuits are clocked by either the Internal Oscillator or an external clock source. When playback is desired the previously stored recording is retrieved from memory, low pass filtered, and amplified as shown on the right hand side of the diagram. The signal can be heard by connecting a speaker to the SP+ and SP- pins. Chip-wide management is accomplished through the device control block shown in the upper right hand corner. Message management is provided through the message control block represented in the lower center of the block diagram. More detail on actual device application can be found in the Sample Application section. More detail on sampling control can be found in the Sample Rate and Voice Quality section. More detail on Message management and device control can be found in the Message Management section.



Tips for better sound replay quality:
1. Use a good quality 8 Ohm speaker with a cavity such as speakers for computer sound systems.
Do not use a bare speaker which gives you degraded sound.
2. For better sound replay quality, speak with a distance to the on-board microphone and speak
clearly. Also keep the background noise as low as possible.
3. For even better sound replay quality, use microphone input or Audio Line In input. If Audio
Line In is used, the amplitude of input signal should be < 100 mV p-p.


Its compact size, higher range and easy usability make it a handy sensor for distance measurement and mapping.
Ultrasonic sensors (also known as transceivers when they both send and receive) work on a principle similar to radar or sonar which evaluate attributes of a target by interpreting the echoes from radio or sound waves respectively. Ultrasonic sensors generate high frequency sound waves and evaluate the echo which is received back by the sensor. Sensors calculate the time interval between sending the signal and receiving the echo to determine the distance to an object.
This technology can be used for measuring: wind speed and direction (anemometer), fullness of a tank and speed through air or water. For measuring speed or direction a device uses multiple detectors and calculates the speed from the relative distances to particulates in the air or water. To measure the amount of liquid in a tank, the sensor measures the distance to the surface of the fluid. Further applications include: humidifiers, sonar, medical ultrasonography, burglar alarms and non-destructive testing. Systems typically use a transducer which generates sound waves in the ultrasonic range, above 20,000 hertz, by turning electrical energy into sound, then upon receiving the echo turn the sound waves into electrical energy which can be measured and displayed. The technology is limited by the shapes of surfaces and the density or consistency of the material. For example foam on the surface of a fluid in a tank could distort a reading.


Sound field of a non focusing 4MHz ultrasonic transducer with a near field length of N=67mm in water. The plot shows the sound pressure at a logarithmic db-scale.
Sound pressure field of the same ultrasonic transducer (4MHz, N=67mm) with the transducer surface having a spherical curvature with the curvature radius R=30mm
An ultrasonic transducer is a device that converts energy into ultrasound, or sound waves above the normal range of human hearing. While technically a dog whistle is an ultrasonic transducer that converts mechanical energy in the form of air pressure into ultrasonic sound waves, the term is more apt to be used to refer to piezoelectric transducers that convert electrical energy into sound. Piezoelectric crystals have the property of changing size when a voltage is applied, thus applying an alternating current (AC) across them causes them to oscillate at very high frequencies, thus producing very high frequency sound waves. The location at which a transducer focuses the sound, can be determined by the active transducer area and shape, the ultrasound frequency and the sound velocity of the propagation medium. The example shows the sound fields of an unfocused and a focusing ultrasonic transducer in water.
Since piezoelectric crystals generate a voltage when force is applied to them, the same crystal can be used as an ultrasonic detector. Some systems use separate transmitter and receiver components while others combine both in a single piezoelectric transceiver.
Alternative methods for creating and detecting ultrasound include magnetostriction and capacitive actuation.


The PING))) sensor detects objects by emitting a short ultrasonic burst and then "listening" for the echo. Under control of a host microcontroller (trigger pulse), the sensor emits a short 40 kHz (ultrasonic) burst. This burst travels through the air at about 1130 feet per second, hits an object and then bounces back to the sensor. The PING))) sensor provides an output pulse to the host that will terminate when the echo is detected, hence the width of this pulse corresponds to the distance to the target.


¢ï Minimum range 10 centimeters
¢ï Maximum range 400 centimeters (4 Meters)
¢ï Accuracy of +-1 cm
¢ï Resolution 0.1 cm
¢ï 5V DC Supply voltage
¢ï Compact sized SMD design
¢ï Modulated at 40 kHz
¢ï Serial data of 9600 bps TTL level output for easy interface with any microcontroller


Pin Details
Output format
The serial output data consist of nine ASCII bytes as per table below
Sample outputs strings


Use in medicine
Medical ultrasonic transducers (probes) come in a variety of different shapes and sizes for use in making pictures of different parts of the body. The transducer may be passed over the surface of the body or inserted into a body opening such as the rectum or vagina. Clinicians who perform ultrasound-guided procedures often use a probe positioning system to hold the ultrasonic transducer.
Use in industry
Ultrasonic sensors are used to detect the presence of targets and to measure the distance to targets in many automated factories and process plants. Sensors with an on or off digital output are available for detecting the presence of objects, and sensors with an analog output which varies proportionally to the sensor to target separation distance are commercially available.
Because ultrasonic sensors use sound rather than light for detection, they work in applications where photoelectric sensors may not. Ultrasonicâ„¢s are a great solution for clear object detection and for liquid level measurement, applications that photoelectric struggle with because of target translucence. Target color and/or reflectivity don't affect ultrasonic sensors which can operate reliably in high-glare environments.[1]
Other types of transducers are used in commercially available ultrasonic cleaning devices. An ultrasonic transducer is affixed to a stainless steel pan which is filled with a solvent (frequently water or isopropanol) and a square wave is applied to it, imparting vibration energy on the liquid.


Here we are using 8 ohms speaker. It is connected to the voce recorder and it spokes out the corresponding voice when ultra sonic sensor detects the obstacle. For example if right side sensor detects some obstacle on its side it sends the signal to the Rabbit processor and program is executed and it sends the signal to voice recorder control and master pin and the voice already recorded in voice recorder will speaks out through the speaker right right right right¦¦.



In this project we have Rabbit processor, three ultra sonic sensors and voice recorder which are connected as shown in the schematic diagram.
Ultra sonic sensor has 3 pins, they are Vcc, Gnd and output pin. The Vcc is given to Vcc of processor in J2 header. The output pin is connected to the port B of processor and these are pulling down with 1k ohms resistors. And Gnd of ultra sonic sensor is connected to Gnd of processor as shown in schematic diagram. Here we are using Port B bits PB0, PB2, PB3. If we observe the pin diagram of Rabbit processor, we donâ„¢t have PB1 bit.
Here to indicate the voice we using voice recorder in which we recording the voice left,
right and front.
Here we are using a condenser which receives the voice which we speak out and converts is to digital i.e., it acts as a transducer and it stores in the memory voice analyzer. It contains 8 pages so we have 8 ways of storing voce. Here we have one master and 8 control pins of which we are using three control pins for left, right and front sensors. Here master is active high and
Control pins are active low.


The RCM3100 module uses the Dynamic C development environment for rapid creation and debugging of runtime applications. Dynamic C provides a complete development environment with integrated editor, compiler and debugger. It interfaces directly with the target system, eliminating the need for complex and unreliable in-circuit emulators. Dynamic C must be installed on a Windows workstation with at least one free serial USB or COM port for communication with the target system.
NOTE: An RS-232/USB converter is required if you intend to use a USB port on your computer. Z-World and Rabbit Semiconductor offer a suitable converter”more information is available at, or you may telephone your Z-World/Rabbit Semiconductor sales representative or authorized distributor.
NOTE: The RCM3100 module requires Dynamic C v7.25 or later for development. A
compatible version is included on the Development Kit CD-ROM.


Dynamic C integrates the following development functions into one program:
¢ Editing
¢ Compiling
¢ Linking
¢ Loading
¢ In-Circuit Debugging
In fact, compiling, linking and loading are one function. Dynamic C does not use an In-
Circuit Emulator; programs being developed are downloaded to and executed from the
target system via an enhanced serial-port connection. Program development and debugging
take place seamlessly across this connection, greatly speeding system development.
Other features of Dynamic C include:
¢ Dynamic C has an easy-to-use built-in text editor. Programs can be executed and
debugged interactively at the source-code or machine-code level. Pull-down menus and
keyboard shortcuts for most commands make Dynamic C easy to use.
¢ Dynamic C also supports assembly language programming. It is not necessary to leave
C or the development system to write assembly language code. C and assembly language
may be mixed together.
¢ Debugging under Dynamic C includes the ability to use printf commands, watch
expressions, breakpoints and other advanced debugging features. Watch expressions
can be used to compute C expressions involving the targetâ„¢s program variables or
functions. Watch expressions can be evaluated while stopped at a breakpoint, single stepping,
or while the target is running its program.
16 Rabbit Core RCM3100
¢ Dynamic C provides extensions to the C language (such as shared and protected variables,
co statements and co functions) that support real-world embedded system development.
Dynamic C supports cooperative and preemptive multi-tasking.
¢ Dynamic C comes with many function libraries, all in source code. These libraries support
real-time programming, machine level I/O, and provide standard string and math
¢ Dynamic C compiles directly to memory. Functions and libraries are compiled and
linked and downloaded on-the-fly. On a fast PC, Dynamic C can load 30,000 bytes of
code in 5 seconds at a baud rate of 115,200 bps.
To install and run Dynamic C, your system must be running one of the following operating
¢ Windows 95
¢ Windows 98
¢ Windows NT
¢ Windows Me
¢ Windows 2000
¢ Windows XP
The PC on which you install Dynamic C for development of RCM3100-based systems
should have the following hardware:
¢ A Pentium or later microprocessor
¢ 32 MB of RAM
¢ At least one free COM (serial) port for communication with the target systems
¢ A CD-ROM drive (for software installation)


Insert the Dynamic C CD-ROM in the drive on your PC. If autorun is enabled, the CD
installation will begin automatically. If autorun is disabled or the installation otherwise does not start, use the Windows Start | Run menu or Windows Disk Explorer to launch SETUP.EXE from the root folder of the CD-ROM. The installation program will guide you through the installation process. Most steps of the process are self-explanatory and not covered in this section. Selected steps that may be confusing to some users are outlined below. (Some of the installation utility screens may vary slightly from those shown.) PROGRAM & DOCUMENTATION FILE LOCATION

Dynamic Câ„¢s application, library and documentation files can be installed in any convenient
location on your workstationâ„¢s hard drives.
The default location, as shown in the example above, is in a folder named for the version of Dynamic C, placed in the root folder of the C: drive. If this location is not suitable, enter a different root path before clicking Next >. Files are placed in the specified folder, so do not set this location to a driveâ„¢s root directory. INSTALLATION TYPE

Dynamic C has two components that can be installed together or separately. One component
is Dynamic C itself, with the development environment, support files and libraries.
The other component is the documentation library in HTML and PDF formats, which may
be left uninstalled to save hard drive space or installed elsewhere (on a separate or network
drive, for example).
The installation type is selected in the installation menu shown above. The options are:
¢ Typical Installation ” Both Dynamic C and the documentation library will be
installed in the specified folder (default).
¢ Compact Installation ” Only Dynamic C will be installed.
¢ Custom Installation ” You will be allowed to choose which components are
installed. This choice is useful to install or reinstall just the documentation. SELECT COM PORT

Dynamic C uses a COM (serial) port to communicate with the target development system.
The installation allows you to choose the COM port that will be used.
The default selection, as shown in the example above, is COM1. You may select any available port for Dynamic Câ„¢s use. If you are not certain which port is available, select COM1.
This selection can be changed later within Dynamic C. DESKTOP ICONS

Once your installation is complete, you will have up to three icons on your PC desktop, as
shown below.
One icon is for Dynamic C, one opens the documentation menu, and the third is for the Rabbit Field Utility, a tool used to download precompiled software to a target system.


Once the RCM3100 is set up and connected as described in Chapter 2 and Dynamic C has
been installed, start Dynamic C by double-clicking on the Dynamic C icon. Dynamic C
should start, then look for the target system on the COM port you specified during installation
(by default, COM1). Once detected, Dynamic C should go through a sequence of
steps to cold-boot the module and compile the BIOS.
If you receive the message beginning "BIOS successfully compiled" you are
ready to continue with the sample programs.
Communication Error Messages
If you receive the message "No Rabbit Processor Detected," the programming
cable may be connected to a different COM port, a connection may be faulty, or the target
system may not be powered up. First, check to see that the power LED on the Prototyping
Board is lit and that the jumper across pins 5“6 of header JP1 on the Prototyping Board is
installed. If the LED is lit, check both ends of the programming cable to ensure that it is
firmly plugged into the PC and the RCM3100 series moduleâ„¢s programming port. If you
are using the Prototyping Board, ensure that the module is firmly and correctly installed in
its connectors.
If there are no faults with the hardware, select a different COM port within Dynamic C.
From the Options menu, select Communications. The dialog shown should appear.
Select another COM port from the list, then click OK. Press <Ctrl-Y> to force Dynamic C to recompile the BIOS. If Dynamic C still reports it is unable to locate the target system, repeat the above steps until you locate the active COM port.
If Dynamic C appears to compile the BIOS successfully, but you then receive a communication
error message, it is possible that your PC cannot handle the 115,200 bps baud rate.
Try changing the baud rate to 57,600 bps as follows.
¢ Locate the Serial Options dialog in the Dynamic C Options > Communications
menu. Change the baud rate to 57,600 bps.


With Dynamic C running, click File > Open, and select Lib. The following list of
Dynamic C libraries will be displayed.
There is no unique library that is specific to the RCM3100. The functions in the above
libraries are described in the Dynamic C Premier Userâ„¢s Manual.
The RCM3100 was designed to interface with other systems, and so there are no drivers
written specifically for the I/O. The general Dynamic C read and write functions allow
you to customize the parallel I/O to meet your specific needs. For example, use
WrPortI(PEDDR, &PEDDRShadow, 0x00);
to set all the Port E bits as inputs, or use
WrPortI(PEDDR, &PEDDRShadow, 0xFF);
to set all the Port E bits as outputs.
When using the auxiliary I/O bus on the Rabbit 3000 chip, add the line
#define PORTA_AUX_IO // required to enable auxiliary I/O bus
to the beginning of any programs using the auxiliary I/O bus.
The sample programs in the Dynamic C SAMPLES/RCM3100 directory provide further
Serial Communication Drivers
Library files included with Dynamic C provide a full range of serial communications support.
The RS232.LIB library provides a set of circular-buffer-based serial functions. The
PACKET.LIB library provides packet-based serial functions where packets can be delimited
by the 9th bit, by transmission gaps, or with user-defined special characters. Both
libraries provide blocking functions, which do not return until they are finished transmitting
or receiving, and no blocking functions, which must be called repeatedly until they
are finished. For more information, see the Dynamic C Premier Userâ„¢s Manual and Technical


Sample programs are provided in the Dynamic C Samples folder, which is shown below
The various folders contain specific sample programs that illustrate the use of the corresponding
Dynamic C libraries. For example, the sample program PONG.C demonstrates
the output to the Dynamic C STDIO window.
One folders contain sample programs that illustrate features unique to the RCM3100.
¢ RCM3100”Demonstrates the basic operation of the RCM3100.
Other sample folders that do not have board names contain genereic sample programs,
which will run on all boards.
Follow the instructions included with the sample program to connect the RCM3100 and
the other hardware identified in the instructions.
To run a sample program, open it with the File menu (if it is not still open), compile it
using the Compile menu (or press F5), and then run it by selecting Run in the Run menu
(or press F9). The RCM3100 must be in Program Mode (see Figure 4) and must be connected
to a PC using the programming cable.


Dynamic C patches that focus on bug fixes are available from time to time. Check the Web sites
¢ http://www.zworldsupport/
¢ http://www.rabbitsemiconductorsupport/
for the latest patches, workarounds, and bug fixes. The default installation of a patch or bug fix is to install the file in a directory (folder) different from that of the original Dynamic C installation. Z-World recommends using a different directory so that you can verify the operation of the patch without overwriting the existing Dynamic C installation. If you have made any changes to the BIOS or to libraries, or if you have programs in the old directory (folder), make these same changes to the BIOS or libraries in the new directory containing the patch. Do not simply copy over an entire file since you may overwrite a bug fix; of course, you may copy over any programs you have written.
Dynamic C SE (Special Edition) versions are designed for use with select Rabbit products,
and are included free as part of our low-cost development kits. Dynamic C SE is a complete
software development system, but does not include all of Dynamic C Premier's features
and upgrade path. Dynamic C Premier includes the popular μC/OS-II real-time
operating system, as well as PPP, Advanced Encryption Standard (AES), and other select
libraries. Dynamic C Premier includes a one-year maintenance agreement for telephone
tech support and an upgrade path for all new releases. Serious users and OEMs are encouraged
to buy Dynamic C Premier.


#define    YES    1
#define    NO        0
nodebug void waitinterval_MSec(unsigned long interval)
int Done;
/* Rewritten to use DelayMs function */
Done = NO;
Done = YES;
if(Done == YES)
void init(void)
BitWrPortI(PDDDR,&PDDDRShadow,1,0); //Master    //Active Low to High to Low
BitWrPortI(PBDDR,&PBDDRShadow,0,0); //Left     //Active High
BitWrPortI(PBDDR,&PBDDRShadow,0,2); //Front      //Active High
BitWrPortI(PBDDR,&PBDDRShadow,0,3);    //Right     //Active High
void init1(void)
    BitWrPortI(PDDDR,&PDDDRShadow,1,1); //rec1    //Active High to Low to High    //Left
BitWrPortI(PDDDR,&PDDDRShadow,1,2); //rec2 //Active High to Low to High //Front
BitWrPortI(PDDDR,&PDDDRShadow,1,3); //rec3 //Active High to Low to High //Right
void reset_vr(void)
    BitWrPortI(PDDR,&PDDRShadow,0,0); //Master //Active Low to High to Low
BitWrPortI(PDDR,&PDDRShadow,1,0); //Master //Active Low to High to Low
BitWrPortI(PDDR,&PDDRShadow,0,0); //Master //Active Low to High to Low
void main()
    while(BitRdPortI(PBDR,0)==0 && BitRdPortI(PBDR,2)==0 && BitRdPortI(PBDR,3)==0);
    printf("Sensor Right\n\n");
BitWrPortI(PDDR,&PDDRShadow,1,1); //rec1    //Active High to Low to High    //Left
BitWrPortI(PDDR,&PDDRShadow,0,1); //rec1    //Active High to Low to High    //Left
BitWrPortI(PDDR,&PDDRShadow,0,0); //Master //Active Low to High to Low
        BitWrPortI(PDDR,&PDDRShadow,1,0); //Master //Active Low to High to Low
BitWrPortI(PDDR,&PDDRShadow,1,1); //rec1    //Active High to Low to High    //Left
BitWrPortI(PDDR,&PDDRShadow,0,0); //Master //Active Low to High to Low
WrPortI(PDDR,&PDDRShadow,0x01); //Master //Active Low to High to Low
    printf("Sensor Frontx\n\n");
BitWrPortI(PDDR,&PDDRShadow,1,2); //rec2    //Active High to Low to High    //Left
BitWrPortI(PDDR,&PDDRShadow,0,2); //rec2    //Active High to Low to High    //Left
BitWrPortI(PDDR,&PDDRShadow,0,0); //Master //Active Low to High to Low
        BitWrPortI(PDDR,&PDDRShadow,1,0); //Master //Active Low to High to Low
BitWrPortI(PDDR,&PDDRShadow,1,2); //rec2    //Active High to Low to High    //Left
BitWrPortI(PDDR,&PDDRShadow,0,0); //Master //Active Low to High to Low
WrPortI(PDDR,&PDDRShadow,0x01); //Master //Active Low to High to Low
    printf("Sensor Front\n\n");
BitWrPortI(PDDR,&PDDRShadow,1,3); //rec3    //Active High to Low to High    //Left
BitWrPortI(PDDR,&PDDRShadow,0,3); //rec3    //Active High to Low to High    //Left
BitWrPortI(PDDR,&PDDRShadow,0,0); //Master //Active Low to High to Low
        BitWrPortI(PDDR,&PDDRShadow,1,0); //Master //Active Low to High to Low
BitWrPortI(PDDR,&PDDRShadow,1,3); //rec3    //Active High to Low to High    //Left
BitWrPortI(PDDR,&PDDRShadow,0,0); //Master //Active Low to High to Low
WrPortI(PDDR,&PDDRShadow,0x01); //Master //Active Low to High to Low


In this project we have Rabbit processor, three ultra sonic sensors and voice recorder which are connected as shown in the block diagram.
Ultra sonic sensor has 3 pins, they are Vcc, Gnd and output pin. The Vcc is given to Vcc of processor in J2 header. The output pin is connected to the port B of processor and these are pulling down with 1k ohms resistors. And Gnd of ultra sonic sensor is connected to Gnd of processor. Here we are using Port B bits PB1, PB2, PB3.
Here to indicate the voice we using voice recorder in which we recording the voice left,
right and front. It consists of condenser, memory IC 9600, filter section, voltage regulator and bridge rectifier section.
Here we are using a condenser which receives the voice which we speak out and converts is to digital i.e., it acts as a transducer and it stores in the memory voice analyzer. It contains 8 pages so we have 8 ways of storing voce. Here we have one master and 8 control pins of which we are using three control pins for left, right and front sensors. Here master is active high and
Control pins are active low. Here we have two modes.
1) Recorder mode
2) Play back mode
Here, In this is recorder, we first press the control and then we trigger the master and then we recorder it for 8 seconds. Here it is manual triggering. Then we use play back mode in which we control via the software using port PD0 “ PD4 pins where 1 pin is used for master and three are for control pins. Here it is software control.
For example when left sensor detects an obstacle on the left side, the transmitted signal will get reflected back. Here the signal from PB0 port will be sent to rabbit processor and the code is executed. Here in the program If loop written for left sensor will be executed and the master pin and corresponding control pin is executed and voice will be speak out by speaker Left Left Left Left¦¦.., which is connected to voice recorder.

We made an attempt to create a prototype for assisting blind people to sense the objects around them so that we can reduce the probability of collisions. More over by using more efficient and reliable components we can make a reliable one which effectively visualizes the blind people.


Z-World, Inc.
2900 Spafford Street
Davis, California 95616-6800
Telephone: (530) 757-3737
Fax: (530) 757-3792
Rabbit Semiconductor
2932 Spafford Street
Davis, California 95616-6800
Telephone: (530) 757-8400
Fax: (530) 757-8402
090-0144 RCM3100 Schematic
090-0137 RCM3000/RCM3100 Prototyping Board Schematic
090-0156 LCD/Keypad Module Schematic
090-0128 Programming Cable Schematic
^ Ultrasonicâ„¢s Basics (Banner Engineering)
en.wikipediawiki/Ultrasonic sensor
Post: #4
Post: #5
thank you so much. .
Post: #6
the theme of project is good. but where do i find the circuit diag? tell me plzzz. now
Post: #7
" please refer the link below
Post: #8


Post: #9
to get information about the topic MULTISENSOR STRATEGIES TO SUPPORT BLIND PEOPLE full report ,ppt and related topic refer the link bellow
Post: #10
can you plss give me the circuit diagram of this model?plsss..
Post: #11
to get information about the topic "MULTISENSOR STRATEGIES TO SUPPORT BLIND PEOPLE-A CLEAR-PATH INDICATOR" full report refer the link bellow

Marked Categories : people, abstract for sensors for blind people, sensor specs for blind people with abstract, simple hardware projects in electronics to help blind people, electronisstrategies to assist blind people, seminar on multi sensor technology for blind people, microprocesser used in stick for bliend man to scence the problem and remove them, multisensor strategies to assist blind people, program to interface the ultrasonic transducers with apr9600, program for interfacing ultrasonic sensor with apr9600, multisensor strategy to assist blind people documentation, circuit diagram for design of multi sensor based path guidance system for blind people assistance,

Quick Reply
Type your reply to this message here.

Image Verification
Image Verification
(case insensitive)
Please enter the text within the image on the left in to the text box below. This process is used to prevent automated posts.

Possibly Related Threads...
Thread: Author Replies: Views: Last Post
  bicycle indicator project report Guest 0 0 11-05-2018 08:11 PM
Last Post: Guest
  design digital rpm indicator for electric motor with over speed alarm indicator Guest 0 0 15-04-2018 06:32 PM
Last Post: Guest
  working principle of brake failure indicator Guest 1 0 07-11-2017 10:47 AM
Last Post: jaseela123
  block diagram of brake failure indicator Guest 1 0 07-11-2017 10:29 AM
Last Post: jaseela123
  physics project for class 12 water level indicator Guest 1 252 13-10-2017 02:05 PM
Last Post: jaseela123
  blind image quality assessment a natural scene statistics approach in the dct domain Guest 1 175 11-10-2017 01:02 PM
Last Post: jaseela123
  digital distance indicator for safe parkin of cars Guest 1 181 10-10-2017 10:24 AM
Last Post: jaseela123
Rainbow seminar ppt for bus alert system for easy navigation of blind using zigbee Guest 1 209 07-10-2017 02:55 PM
Last Post: jaseela123
  marketing strategies of airtel and its impacts on customer buying behaviour Guest 1 158 07-10-2017 10:20 AM
Last Post: jaseela123
  blind man stick test case Guest 1 215 07-10-2017 09:14 AM
Last Post: jaseela123