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Optimization of Delta-Sigma ADC for Column-Level Data Conversion
Post: #1

Optimization of Delta-Sigma ADC for Column-Level Data Conversion in CMOS Image Sensors


.ppt  IMTC_2007_MJ.ppt (Size: 553.5 KB / Downloads: 34)

Solution (delta-sigma ADC)

Unlike Nyquist rate ADCs, oversampled ADCs (delta-sigma ADC) can filter the temporal noise in array sensors, achieving higher SNR.
Delta-sigma ADC is very tolerant to nonidealities of CMOS circuits.
Flexibility of trading the number of bits-per-pixel, with the frame rate in delta-sigma ADC is another advantage.
A few works have designed the DS-ADC for column or pixel level but with large power and area usage.
Main issue of DS-ADC is power consumption and area usage which should be minimized (subject of this work).


ADC structure in image sensors

Chip level ADC (One ADC for all of the pixels)
High spatial resolution
But, high noise, high power, fast ADC is needed,
Pixel level ADC (One ADC for each pixel or group of pixels)
Low noise, low speed ADC is needed, low power
But, low spatial resolution, high FPN.
Column level ADC (One ADC for each column or group of columns)
A compromise between pixel level and chip level.
In this work a first-order column-level delta-sigma ADC will be designed.


Operational Transconductance Amplifier


OTA is the most critical Component
Folded-cascode OTA structure with gain boosting was used.


DDA-CMFB circuit.


OTA needs a common-mode feedback (CMFB) circuit .
(1) Switched capacitor CMFB
It has large swing and linearity.
Loads the output of the OTA, reducing its UGB and SLR.Large area is needed
(2) We used a differential-difference amplifier CMFB (DDA-CMFB).
It can offer enough swing and linearity with very small area.
Post: #2
A delta-sigma analog-to-digital converter (ADC) is designed, optimized and simulated for converting column-level data into a CMOS image sensor. For a 0.18 mm process, the design reaches 80 dB signal-to-noise ratio (SNR), including a 10 dB margin for non-simulated kTC noise, and consumes 210 muW of power at a sampling frequency of 50 kHz . The low power is mainly realized using a architecture of first order and minimizing the capacitors. For the modulator, an optimized cascade folded-helmet (OTA) transconductance amplifier is optimized to achieve a gain of 90 dB with a unit gain bandwidth of 300 MHz. The decimator is also optimized by placing part of the circuit in the level of chip. Zero distortion is possible in the decimator due to the discrete time nature of the input signal. The proposed ADC allows a reduction in reading non-linearity of a CMOS image sensor, which allows a high SNR to be performed.
 

Marked Categories : folded cascode, delta sigma modulator ppt, column level sigma delta adc pixel sensor,

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