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Razor Technology
Post: #1

A code sign methodology incorporates timing speculation into a low-power microprocessor pipeline and shaves energy levels far below the point permitted by worst-case computation paths.

An old adage says, "If you're not failing some of the time, you're not trying hard enough." To address the power challenges that current on-chip densities pose, we adapted this precept to circuit design. Razor,(1) a voltage-scaling technology based on dynamic detection and correction of circuit timing errors, permits design optimizations that tune the energy in a microprocessor pipeline to typical circuit operational levels. This eliminates the voltage margins that traditional worst-case design methodologies require and allows digital systems to run correctly and robustly at the edge of minimum power consumption.

Occasional heavy weight computations may fail and require additional time and energy for recovery, but the overall computation in the optimized pipeline requires significantly less energy than traditional designs.

Razor supports timing speculation through a combination of architectural and circuit techniques, which we have implemented in a prototype Razor pipeline in 0.18-micrometer technology. Simulation results of the SPEC 2000 benchmarks showed energy savings for every benchmark, up to a 64 percent savings with less than 3 percent performance impact for error recovery.


Both circuit speed and energy dissipation depend on voltage. The speed or clock frequency, f of a digital circuit
is proportional to the supply voltage, Vdd:
f ? Vdd
The energy E necessary to operate a digital circuit for a time duration T is the sum of two energy components:
E = SCV2dd + VddIleakT
where the first term models the dynamic power lost from charging and discharging the capacitive loads within the circuit and the second term models the static power lost in passive leakage current-that is, the small amount of current that leaks through transistors even when they are turned off.

The dynamic power loss depends on the total number of signal transitions, S, the total capacitance load of the circuit wire and gates, C, and the square of the supply voltage. The static power loss depends on the supply voltage, the rate of current leakage through the circuit, Ileak , and the duration of operation during which leakage occurs, T.

2.1 Dynamic Voltage Scaling
Dynamic voltage scaling has emerged as a powerful technique to reduce circuit energy demands. In a DVS system, the application or operating system identifies periods of low processor utilization that can tolerate reduced frequency. With reduced frequency, similar reductions are possible in the supply voltage. Since dynamic power scales quadratically with supply voltage, DVS technology can significantly reduce energy consumption with little impact on perceived system performance.

2.2 Error-Tolerant DVS

Razor is an error-tolerant DVS technology. Its error- tolerance mechanisms eliminate the need for voltage margins that designing for "always correct" circuit operations requires. The improbability of the worst-case conditions that drive traditional circuit design underlies the technology.

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