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 verilog code to implement nikhilam sutra

sir ,
I need mac unit design using vedic multiplier(nikilam sutra) and adder should be designed using reversible logic . I need verilog code for the above mentioned project.
Nikhilam sutra is an ancient Vedic multiplication algorithm that avoids the need for large multipliers by reducing the multiplication of large numbers to that of smaller numbers. This considerably reduces the propagation delay associated with large conventional multipliers. The project involves the development and implementation of Nikhilam sutra using Verilog. This work is dedicated to the design and FPGA implementation of a 16-bit multiplier, which It uses Vedic Mathematical Algorithms. In this thesis work , formulate this (VEDIC) math to design The multiplier architecture with two clear goals in mind Such as:
i) Simplicity and multiplication of modularity For VLSI implementations and
ii) Area Reduction
Iii) Reduction of delays.
Vedic mathematics and its application to the Multiplier guarantees a substantial reduction of Delay compared to architecture based on Implementation based on parallel adder that are Architectures commonly used. For arithmetic Multiplication of various Vedic multiplication techniques As Urdhvatiryakbhyam, Nikhilam, has been found That the proposed multiplier using Nikhilam Sutra is the majority Sutra (Algorithm), with a minimum delay for Multiplication of all types of numbers, either
In addition, the Verilog HDL encoding of Urdhvatiryakbhyam Sutra for 16 bits, zikhialm Sutra For 16 bits and Verilog code of the proposed multiplier Using Nikhilam Sutra for 16 bits, and synthesize Results show that, the combinational delay for Multiplier The use of nikhilam Sutra is 23.751ns, and for Multiplier Use UrdhvaTiryagbhyam Sutra is 15.953ns, but While the combinational delay for the proposed multiplier The use of nikhialm sutra is 13.118ns, which shows that
There is a 47% increase in combinational delay.
(03-02-2017, 11:22 AM)jaseela123 Wrote: Nikhilam sutra is an ancient Vedic multiplication algorithm that avoids the need for large multipliers by reducing the multiplication of large numbers to that of smaller numbers. This considerably reduces the propagation delay associated with large conventional multipliers. The project involves the development and implementation of Nikhilam sutra using Verilog. This work is dedicated to the design and FPGA implementation of a 16-bit multiplier, which It uses Vedic Mathematical Algorithms. In this thesis work , formulate this (VEDIC) math to design The multiplier architecture with two clear goals in mind Such as:
i) Simplicity and multiplication of modularity For VLSI implementations and
ii) Area Reduction
Iii) Reduction of delays.
Vedic mathematics and its application to the Multiplier guarantees a substantial reduction of Delay compared to architecture based on Implementation based on parallel adder that are Architectures commonly used. For arithmetic Multiplication of various Vedic multiplication techniques As Urdhvatiryakbhyam, Nikhilam, has been found That the proposed multiplier using Nikhilam Sutra is the majority Sutra (Algorithm), with a minimum delay for Multiplication of all types of numbers, either
In addition, the Verilog HDL encoding of Urdhvatiryakbhyam Sutra for 16 bits, zikhialm Sutra For 16 bits and Verilog code of the proposed multiplier Using Nikhilam Sutra for 16 bits, and synthesize Results show that, the combinational delay for Multiplier The use of nikhilam Sutra is 23.751ns, and for Multiplier Use UrdhvaTiryagbhyam Sutra is 15.953ns, but While the combinational delay for the proposed multiplier The use of nikhialm sutra is 13.118ns, which shows that
There is a 47% increase in combinational delay.
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