Important: Use custom search function to get better results from our thousands of pages

Use " " for compulsory search eg:"electronics seminar" , use -" " for filter something eg: "electronics seminar" -"/tag/" (used for exclude results from tag pages)


 
 
Thread Rating:
  • 0 Votes - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
verilog code to implement nikhilam sutra
Post: #1

sir ,
I need mac unit design using vedic multiplier(nikilam sutra) and adder should be designed using reversible logic . I need verilog code for the above mentioned project.
Post: #2
Nikhilam sutra is an ancient Vedic multiplication algorithm that avoids the need for large multipliers by reducing the multiplication of large numbers to that of smaller numbers. This considerably reduces the propagation delay associated with large conventional multipliers. The project involves the development and implementation of Nikhilam sutra using Verilog. This work is dedicated to the design and FPGA implementation of a 16-bit multiplier, which It uses Vedic Mathematical Algorithms. In this thesis work , formulate this (VEDIC) math to design The multiplier architecture with two clear goals in mind Such as:
i) Simplicity and multiplication of modularity For VLSI implementations and
ii) Area Reduction
Iii) Reduction of delays.
Vedic mathematics and its application to the Multiplier guarantees a substantial reduction of Delay compared to architecture based on Implementation based on parallel adder that are Architectures commonly used. For arithmetic Multiplication of various Vedic multiplication techniques As Urdhvatiryakbhyam, Nikhilam, has been found That the proposed multiplier using Nikhilam Sutra is the majority Sutra (Algorithm), with a minimum delay for Multiplication of all types of numbers, either
In addition, the Verilog HDL encoding of Urdhvatiryakbhyam Sutra for 16 bits, zikhialm Sutra For 16 bits and Verilog code of the proposed multiplier Using Nikhilam Sutra for 16 bits, and synthesize Results show that, the combinational delay for Multiplier The use of nikhilam Sutra is 23.751ns, and for Multiplier Use UrdhvaTiryagbhyam Sutra is 15.953ns, but While the combinational delay for the proposed multiplier The use of nikhialm sutra is 13.118ns, which shows that
There is a 47% increase in combinational delay.
Post: #3
(03-02-2017 11:22 AM)jaseela123 Wrote:  Nikhilam sutra is an ancient Vedic multiplication algorithm that avoids the need for large multipliers by reducing the multiplication of large numbers to that of smaller numbers. This considerably reduces the propagation delay associated with large conventional multipliers. The project involves the development and implementation of Nikhilam sutra using Verilog. This work is dedicated to the design and FPGA implementation of a 16-bit multiplier, which It uses Vedic Mathematical Algorithms. In this thesis work , formulate this (VEDIC) math to design The multiplier architecture with two clear goals in mind Such as:
i) Simplicity and multiplication of modularity For VLSI implementations and
ii) Area Reduction
Iii) Reduction of delays.
Vedic mathematics and its application to the Multiplier guarantees a substantial reduction of Delay compared to architecture based on Implementation based on parallel adder that are Architectures commonly used. For arithmetic Multiplication of various Vedic multiplication techniques As Urdhvatiryakbhyam, Nikhilam, has been found That the proposed multiplier using Nikhilam Sutra is the majority Sutra (Algorithm), with a minimum delay for Multiplication of all types of numbers, either
In addition, the Verilog HDL encoding of Urdhvatiryakbhyam Sutra for 16 bits, zikhialm Sutra For 16 bits and Verilog code of the proposed multiplier Using Nikhilam Sutra for 16 bits, and synthesize Results show that, the combinational delay for Multiplier The use of nikhilam Sutra is 23.751ns, and for Multiplier Use UrdhvaTiryagbhyam Sutra is 15.953ns, but While the combinational delay for the proposed multiplier The use of nikhialm sutra is 13.118ns, which shows that
There is a 47% increase in combinational delay.
 


[-]
Quick Reply
Message
Type your reply to this message here.

Image Verification
Image Verification
(case insensitive)
Please enter the text within the image on the left in to the text box below. This process is used to prevent automated posts.

Possibly Related Threads...
Thread: Author Replies: Views: Last Post
  msf desalination matlab code Guest 0 0 08-10-2018 05:01 PM
Last Post: Guest
  automatic timetable generator for collage source code in php Guest 0 0 10-09-2018 09:57 AM
Last Post: Guest
  matlab code for iris recognition using wavelets Guest 0 0 11-05-2018 07:49 AM
Last Post: Guest
  leaky bucket source code in opengl Guest 0 0 02-05-2018 05:58 PM
Last Post: Guest
  opengl code for leaky bucket Guest 0 0 02-05-2018 06:43 AM
Last Post: Guest
  leaky bucket source code in opengl Guest 0 0 24-04-2018 08:13 PM
Last Post: Guest
Information java source code for video steganography tina28 4 6,320 20-04-2018 07:29 PM
Last Post: Guest
  opengl code for leaky bucket Guest 0 0 19-02-2018 05:23 PM
Last Post: Guest
  column bypassing multiplier code verilog Guest 1 0 01-02-2018 10:52 AM
Last Post: dhanabhagya
  dadda multiplier verilog code Guest 2 3,353 29-01-2018 10:32 AM
Last Post: dhanabhagya
This Page May Contain What is verilog code to implement nikhilam sutra And Latest Information/News About verilog code to implement nikhilam sutra,If Not ...Use Search to get more info about verilog code to implement nikhilam sutra Or Ask Here

Options: